S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 31

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

3.15
March 7, 2013 S34ML01G1_04G1_15
Multiplane Cache Program — S34ML02G1 and S34ML04G1
If the system monitors the progress of the operation only with R/B#, the last page of the target program
sequence must be programmed with Page Program Confirm command (10h). If the Cache Program
command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is
finished before starting any other operation. See
details.
If a Cache Program operation is interrupted by hardware reset, power failure or other means, the host must
ensure that the interrupted pages are not used for further reading or programming operations until the next
uninterrupted block erases are complete for the applicable blocks.
The Multiplane Cache Program enables high program throughput by programming two pages in parallel,
while exploiting the data and cache registers of both planes to implement cache.
The command sequence can be summarized as follows:
 Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st
 The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes
 Once device returns to ready again, 81h command must be issued, followed by 2nd page address
 Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command
The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and each time the device will be busy for the
t
data from the cache registers. The sequence to end Multiplane Cache Program is 80h-...- 11h...-...81h...-
...10h.
The Multiplane Cache Program is available only within two paired blocks in separate planes.
on page 59
address bits for the first plane are all zero and the second address issued selects the block for both planes.
Figure 6.33 on page 60
addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select the
plane.
The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user
opts for 70h, Read Status Register will provide “global” information about the operation in the two planes.
 I/O6 indicates when both cache registers are ready to accept new data.
 I/O5 indicates when the cell programming of the current data registers is complete.
 I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not.
 I/O0 identifies if any error has been detected by the program/erase controller while programming the two
See
If the system monitors the progress of the operation only with R/B#, the last pages of the target program
sequence must be programmed with Page Program Confirm command (10h). If the Cache Program
command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is
finished before starting any other operation. Refer to
CBSYW
page. Address for this page must be within 1st plane (PLA0 = 0). The data of 1st page other than those to
be programmed do not need to be loaded. The device supports Random Data Input exactly like Page
Program operation.
busy for a short time (t
(5 cycles) and its serial data input. Address for this page must be within 2nd plane (PLA0 = 1). The data of
2nd page other than those to be programmed do not need to be loaded.
register, the data in the cache registers is transferred into the data registers for cell programming. At this
time the device remains in the Busy state for a short time (t
are transferred into the data registers, the device returns to the Ready state, and allows loading the next
data into the cache register through another cache program command sequence.
This status bit is valid upon I/O6 status bit changing to 1.
pages N. This status bit is valid upon I/O5 status bit changing to 1.
Table 3.5 on page 29
time needed to complete programming the current data register contents, and transferring the new
shows the legacy protocol for the multiplane cache program operation. In this case, the block
shows the ONFI protocol for the multiplane cache program operation. For both
D a t a
DBSY
for more details.
Spansion
).
S h e e t
®
SLC NAND Flash Memory for Embedded
Table 3.5 on page 29
Section 3.9 on page 28
CBSYW
). After all data from the cache registers
and
Figure 6.31 on page 58
for further information.
Figure 6.32
for more
31