S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 43

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

5.7
6. Timing Diagrams
6.1
March 7, 2013 S34ML01G1_04G1_15
Program / Erase Characteristics
Command Latch Cycle
Notes:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed (V
2. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the
Command Input bus operation is used to give a command to the memory device. Commands are accepted
with Chip Enable low, Command Latch Enable High, Address Latch Enable low, and Read Enable High and
latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/
erase) the Write Protect pin must be high.
Program Time / Multiplane Program Time
Dummy Busy Time for Two Plane Program (S34ML02G1, S34ML04G1)
Cache Program short busy time (S34ML02G1, S34ML04G1)
Number of partial Program Cycles in the same page
Block Erase Time / Multiplane Erase Time (S34ML02G1, S34ML04G1)
Block Erase Time (S34ML01G1)
Read Cache busy time
device to meet the program time (t
address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page
(target page).
WE#
CLE
CE#
ALE
I/Ox
D a t a
Spansion
Parameter
PROG
Table 5.7 Program / Erase Characteristics
(2)
) specification. Copy Back Program may not meet this specification when copying from an odd
S h e e t
®
Figure 6.1 Command Latch Cycle
SLC NAND Flash Memory for Embedded
tALS
tCLS
tCS
tWP
tDS
Command
Main + Spare
tCLH
tCH
Array
tDH
tALH
Description
t
t
t
CBSYW
t
t
t
CBSYR
NOP
PROG
DBSY
BERS
BERS
Min
—
—
—
—
—
—
—
Typ
200
0.5
3.5
—
5
2
3
CC
= 3.3V, 25°C).
t
Max
PROG
700
10
t
1
4
3
R
Cycle
Unit
ms
ms
µs
µs
µs
µs
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