S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 15

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S34ML02G100BHI003

Manufacturer Part Number
S34ML02G100BHI003
Description
Flash 2G, 3V, 25ns NAND Flash
Manufacturer
Spansion
Datasheet

Specifications of S34ML02G100BHI003

Rohs
yes
Data Bus Width
1 bit
Memory Type
NAND Flash
Memory Size
2 Gbit
Architecture
Sectored
Timing Type
Asynchronous
Access Time
25 ns
Supply Voltage - Max
3.6 V
Supply Voltage - Min
2.7 V
Maximum Operating Current
40 mA
Operating Temperature
- 40 C to + 85 C
Mounting Style
SMD/SMT
Package / Case
BGA-63
Organization
2048 B x 8, 2048 B x 16
1.6
March 7, 2013 S34ML01G1_04G1_15
1.6.1
Addressing
S34ML01G1
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. BAx = Block Address bit.
4. Block address concatenated with page address = actual page address.
5. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the x8 address bits, the following rules apply:
 A0 - A11: column address in the page
 A12 - A17: page address in the block
 A18 - A27: block address
For the x16 address bits, the following rules apply:
 A0 - A10: column address in the page
 A11 - A16: page address in the block
 A17 - A26: block address
Bus Cycle
2nd
2nd
3rd
3rd
1st
4th
1st
4th
I/O [15:8]
Low
Low
Low
Low
(5)
D a t a
A20 (BA2)
A19 (BA2)
A12 (PA0)
A11 (PA0)
A0 (CA0)
A8 (CA8)
A0 (CA0)
A8 (CA8)
Spansion
I/O0
Table 1.3 Address Cycle Map — 1 Gb Device
S h e e t
®
A21 (BA3)
A20 (BA3)
A13 (PA1)
A12 (PA1)
A1 (CA1)
A9 (CA9)
A1 (CA1)
A9 (CA9)
SLC NAND Flash Memory for Embedded
I/O1
A10 (CA10) A11 (CA11)
A10 (CA10)
A22 (BA4)
A21 (BA4)
A14 (PA2)
A13 (PA2)
A2 (CA2)
A2 (CA2)
I/O2
x16
x8
A15 (PA3)
A23 (BA5)
A14 (PA3)
A22 (BA5)
A3 (CA3)
A3 (CA3)
I/O3
Low
A24 (BA6)
A23 (BA6)
A16 (PA4)
A15 (PA4)
A4 (CA4)
A4 (CA4)
I/O4
Low
Low
A25 (BA7)
A24 (BA7)
A17 (PA5)
A16 (PA5)
A5 (CA5)
A5 (CA5)
I/O5
Low
Low
A18 (BA0)
A26 (BA8)
A17 (BA0)
A25 (BA8)
A6 (CA6)
A6 (CA6)
I/O6
Low
Low
A19 (BA1)
A27 (BA9)
A18 (BA1)
A26 (BA9)
A7 (CA7)
A7 (CA7)
I/O7
Low
Low
15

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