S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 27

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

March 7, 2013 S34ML01G1_04G1_15
3.8.1
Read EDC Status Register — S34ML02G1 and S34ML04G1
For the case of Copy Back Program or Multiplane Copy Back Program operations:
 If Random Data Input is applied in a given EDC unit, the entire EDC unit must be written to the page buffer.
 “Random Data Input” in a given EDC unit can be executed several times during one Copy Back Program
If you use copy back without EDC check, none of the limitations described above apply.
After a Copy Back Program operation, the host can use Read EDC Status Register to check the status of
both the program operation and the Copy Back Read. If the EDC was valid and an error was reported in the
EDC (see
attempt the Copy Back Program again. If this also fails, the host can execute a Page Read operation in order
to correct a single bit error with external ECC software or hardware.
This operation is available only after issuing a Copy Back Program and it allows the detection of errors during
Copy Back Read. In the case of multiplane copy back, it is not possible to know which of the two read
operations caused the error.
After writing the Read EDC Status Register command (7Bh) to the command register, a read cycle outputs
the content of the EDC Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last.
The operation is the same as the Read Status Register command. Refer to
Register definitions:
In other words, the EDC check is possible only if the whole EDC unit is modified during one Copy Back
Program sequence.
sequence, but data insertion in each column address of the EDC unit must not exceed 1.
(1st sector)
256 words
512 byte
“A” area
Table 3.2 on page
ID
0
1
2
3
4
5
6
7
(2nd sector)
256 words
Main Field (2048 Byte)
512 byte
“B” area
D a t a
Spansion
27), the host may perform Special Read For Copy Back on the source page and
(3rd sector)
Copy Back Program
256 words
512 byte
“C” area
Table 3.3 Page Organization in EDC Units
Ready / Busy
Ready / Busy
Write Protect
EDC validity
S h e e t
EDC status
Pass / Fail
®
Table 3.2 EDC Register Coding
SLC NAND Flash Memory for Embedded
NA
NA
(4th sector)
256 words
512 byte
“D” area
x16
x8
(1st sector)
“E” area
8 words
16 byte
Protected: 0; Not Protected: 1
(2nd sector)
“F” area
8 words
16 byte
Spare Field (64 Byte)
No error: 0; Error: 1
Invalid: 0; Valid: 1
Busy: 0; Ready: 1
Busy: 0; Ready: 1
Table 3.2
Pass: 0; Fail: 1
Coding
—
—
(3rd sector)
for specific EDC
“G” area
8 words
16 byte
(4th sector)
“H” area
8 words
16 byte
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