S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 21

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

3.1
3.2
March 7, 2013 S34ML01G1_04G1_15
Page Read
Page Program
Page Read is initiated by writing 00h and 30h to the command register along with five address cycles
(S34ML02G1 and S34ML04G1). Two types of operations are available: random read and serial page read.
Random read mode is enabled when the page address is changed. The 2112 bytes (x8) or 1056 words (x16)
of data within the selected page are transferred to the data registers in less than 25 µs (t
controller may detect the completion of this data transfer (t
data in a page is loaded into the data registers, they may be read out in 25 ns (x8) or 40 ns (x16) cycle time
by sequentially pulsing RE#. The repetitive high to low transitions of the RE# signal makes the device output
the data, starting from the selected column address up to the last column address.
The device may output random data in a page instead of the sequential data by writing Random Data Output
command. The column address of next data, which is going to be out, may be changed to the address that
follows Random Data Output command. Random Data Output can be performed as many times as needed.
After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation.
Any operation other than read or Random Data Output causes the device to exit read mode.
See
A page program cycle consists of a serial data loading period in which up to 2112 bytes (x8) or 1056 words
(x16) of data may be loaded into the data register, followed by a non-volatile programming period where the
loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five
cycle address inputs (four cycles for S34ML01G1) and then serial data. The words other than those to be
programmed do not need to be loaded. The device supports Random Data Input within a page. The column
address of next data, which will be entered, may be changed to the address that follows the Random Data
Input command (85h). Random Data Input may be performed as many times as needed.
The Page Program confirm command (10h) initiates the programming process. The internal write state
controller automatically executes the algorithms and controls timings necessary for program and verify,
thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read
the Status Register. The system controller can detect the completion of a program cycle by monitoring the
R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or
Reset command are valid while programming is in progress. When the Page Program is complete, the Write
Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully
programmed to 0’s. The command register remains in Read Status command mode until another valid
command is written to the command register.
sequence.
The device is programmable by page, but it also allows multiple partial page programming of a word or
consecutive bytes up to 2112 bytes (x8) or 1056 words (x16) in a single page program cycle.
The number of consecutive partial page programming operations (NOP) within the same page must not
exceed the number indicated in
within a block.
Users who use “EDC check” (for S34ML02G1 and S34ML04G1 only) in copy back must comply with some
limitations related to data handling during one page program sequence. Refer to
details.
If a Page Program operation is interrupted by hardware reset, power failure or other means, the host must
ensure that the interrupted page is not used for further reading or programming operations until the next
uninterrupted block erase is complete.
Figure 6.6 on page 46
D a t a
Spansion
and
Figure 6.12 on page 49
Table 5.7 on page
S h e e t
®
SLC NAND Flash Memory for Embedded
Figure 6.9 on page 47
43. In addition, pages must be sequentially programmed
as references.
R
) by analyzing the output of the R/B pin. Once the
and
Figure 6.11 on page 48
Section 3.8 on page 26
R
). The system
detail the
for
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