S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 28

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

3.9
3.10
28
Read Status Register
Read Status Enhanced — S34ML02G1 and S34ML04G1
The Status Register is used to retrieve the status value for the last operation issued. After writing 70h
command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on
the falling edge of CE# or RE#, whichever occurs last. This two-line control allows the system to poll the
progress of each device in multiple memory connections even when R/B# pins are common-wired. Refer to
Section 3.5 on page 29
on page 55
If the Read Status Register command is issued during multiplane operations then Status Register polling will
return the combined status value related to the outcome of the operation in the two planes according to the
following table:
In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
The command register remains in Status Read mode until further commands are issued. Therefore, if the
Status Register is read during a random read cycle, the read command (00h) should be given before starting
read cycles.
Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack
configurations (single CE#). “Read Status Enhanced” shall be used instead.
Read Status Enhanced is an additional feature used to retrieve the status value for a previous operation in
the case of multiplane operations in the same die.
Figure 6.25 on page 55
must be specified in the command sequence in order to retrieve the status of the die and the plane of interest.
Refer to
mode until further commands are issued.
The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
2nd 256-word Sector
3rd 256-word Sector
2nd 528-byte Sector
1st 256-word Sector
4th 256-word Sector
3rd 528-byte Sector
4th 528-byte Sector
1st 528-byte Sector
Table 3.5
Sector
for timings.
Spansion
for specific Status Register definitions. The command register remains in Status Read
Bit 1, Cache Pass/Fail
Status Register Bit
®
Bit 0, Pass/Fail
for specific Status Register definition, and to
defines the Read Status Enhanced behavior and timings. The plane and die address
SLC NAND Flash Memory for Embedded
Table 3.4 Page Organization in EDC Units by Address
Area Name
Main Field (Column 0-2047)
C
D
D
A
B
A
B
C
D a t a
Column Address
1024-1535
1536-2047
512-1023
768-1023
x16
256-511
512-767
x8
0-511
0-255
S h e e t
Figure 6.22 on page 54
Area Name
S34ML01G1_04G1_15 March 7, 2013
Composite Status Value
Spare Field (Column 2048-2111)
E
G
H
E
G
H
F
F
OR
OR
Column Address
and
2048-2063
2064-2079
2080-2095
2096-2111
1024-1031
1032-1039
1040-1047
1048-1055
Figure 6.24