S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 18

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

1.7
2. Bus Operation
2.1
2.2
18
Mode Selection
Command Input
Address Input
Notes:
1. X can be V
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. During Busy Time in Read, RE# must be held high to prevent unintended data out.
There are six standard bus operations that control the device: Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby. (See
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory
and do not affect bus operations.
The Command Input bus operation is used to give a command to the memory device. Commands are
accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read Enable
high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation
(program/erase) the Write Protect pin must be high. See
details of the timing requirements. Command codes are always applied on I/O7:0 regardless of the bus
configuration (x8 or x16).
The Address Input bus operation allows the insertion of the memory address. For the S34ML02G1 and
S34ML04G1 devices, five write cycles are needed to input the addresses. For the S34ML01G1, four write
cycles are needed to input the addresses. If necessary, a 5th dummy address cycle can be issued to
S34ML01G1, which will be ignored by the NAND device without causing problems. Addresses are accepted
with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read Enable high and
latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/
erase) the Write Protect pin must be high. See
the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus configuration (x8 or
x16). Refer to
Read Mode
Program or Erase Mode
Data Input
Data Output (on going)
Data Output (suspended)
Busy Time in Read
Busy Time in Program
Busy Time in Erase
Write Protect
Stand By
Mode
IL
or V
Spansion
Table 1.3
IH
. H = Logic level HIGH. L = Logic level LOW.
®
through
SLC NAND Flash Memory for Embedded
Command Input
Address Input
Command Input
Address Input
Table 1.5 on page 17
Table 1.6 Mode Selection
D a t a
CLE
High
High
Low
Low
Low
Low
Figure 6.2 on page 44
Table
X
X
X
X
X
X
1.6.)
for more detailed information.
S h e e t
Figure 6.1 on page 43
ALE
High
High
Low
Low
Low
Low
X
X
X
X
X
X
CE#
High
Low
Low
Low
Low
Low
Low
and
X
X
X
X
X
S34ML01G1_04G1_15 March 7, 2013
Table 5.4 on page 41
Rising
Rising
Rising
Rising
Rising
and
WE#
High
High
X
X
X
X
X
Table 5.4 on page 41
High
Falling
High
High
High
High
High
High
RE#
X
X
X
X
(3)
for details of
0V / V
WP#
High
High
High
High
High
Low
X
X
X
X
X
CC
for
(2)