S34ML02G100BHI003 Spansion, S34ML02G100BHI003 Datasheet - Page 29

• Manufacturer Part Number: S34ML02G100BHI003
• Description: Flash 2G, 3V, 25ns NAND Flash
• Manufacturer: Spansion

Specifications of S34ML02G100BHI003

• Rohs: yes
• Data Bus Width: 1 bit
• Memory Type: NAND Flash
• Memory Size: 2 Gbit
• Architecture: Sectored
• Timing Type: Asynchronous
• Access Time: 25 ns
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 2.7 V
• Maximum Operating Current: 40 mA
• Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: BGA-63
• Organization: 2048 B x 8, 2048 B x 16

3.11
3.12
3.13
March 7, 2013 S34ML01G1_04G1_15
Read Status Register Field Definition
Reset
Read Cache
Table 3.5
(S34ML02G1 and S34ML04G1).
The Reset feature is executed by writing FFh to the command register. If the device is in Busy state during
random read, program, or erase mode, the Reset operation will abort these operations. The contents of
memory cells being altered are no longer valid, as the data may be partially programmed or erased. The
command register is cleared to wait for the next command, and the Status Register is cleared to value E0h
when WP# is high or value 60h when WP# is low. If the device is already in reset state a new Reset
command will not be accepted by the command register. The R/B# pin transitions to low for t
Reset command is written. Refer to
be read to determine the status of a Reset operation.
Read Cache can be used to increase the read operation speed, as defined in
cannot cross a block boundary. As soon as the user starts to read one page, the device automatically loads
the next page into the cache register. Serial data output may be executed while data in the memory is read
into the cache register. Read Cache is initiated by the Page Read sequence (00-30h) on a page M.
After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6
switches to high), two command sequences can be used to continue read cache:
 Read Cache (command ‘31h’ only): once the command is latched into the command register (see
 Read Cache Enhanced (sequence ‘00h’ <page N address> ‘31’): once the command is latched into the
Figure 6.28 on page
transferred from the data register to the cache register. At the end of this phase, the cache register data
can be output by toggling RE# while the next page (page address M+1) is read from the memory array into
the data register.
command register (see
data of the first page is transferred from the data register to the cache register. At the end of this phase,
cache register data can be output by toggling RE# while page N is read from the memory array into the
data register.
Note: The S34ML01G1 device does not support Read Cache Enhanced.
ID
0
1
2
3
4
5
6
7
below lists the meaning of each bit of the Read Status Register and Read Status Enhanced
Ready / Busy
Ready / Busy
Write Protect
Reprogram
Program /
Pass / Fail
Page
Page
NA
NA
NA
NA
57), device goes busy for a short time (t
D a t a
Figure 6.29 on page
Spansion
Ready / Busy
Ready / Busy
Block Erase
Write Protect
Pass / Fail
NA
NA
NA
NA
S h e e t
Figure 6.26 on page 56
®
Table 3.5 Status Register Coding
SLC NAND Flash Memory for Embedded
57), device goes busy for a short time (t
Ready / Busy
Ready / Busy
Write Protect
Read
NA
NA
NA
NA
NA
for further details. The Status Register can also
Ready / Busy
Ready / Busy
Write Protect
Read Cache
CBSYR
NA
NA
NA
NA
NA
), during which data of the first page is
Ready / Busy
Ready / Busy
Write Protect
Reprogram
Program /
Pass / Fail
Pass / Fail
Section 3.1 on page
Cache
Cache
NA
NA
NA
CBSYR
Internal Data Operation
Not Protected: 1
RST
), during which
Ready/Busy
Protected: 0
N - 1 Page
Ready: 1
Active: 0
Coding
N Page
Pass: 0
Pass: 0
Busy: 0
Fail: 1
Fail: 1
Idle: 1
after the
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—
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21, and it
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