COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 171

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

Instruction Cycle Time (t
External CKI Clock Duty Cycle (Note 6)
Inputs
Output Propagation Delay (Note 5)
MICROWIRE Setup Time (t
MICROWIRE Hold Time (t
MICROWIRE Output Propagation Delay (t
MICROWIRE Maximum Shift Clock
Input Pulse Width (Note 6)
Reset Pulse Width
t
Note 1: Maximum rate of voltage change must be < 0.5 V/ms.
Note 2: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI,
inputs connected to V
Note 3: The HALT mode will stop CKI from oscillating in the R/C and the Crystal configurations. In the R/C configuration, CKI is forced
high internally. In the crystal or external configuration, CKI is TRI-STATE. Measurement of I
nor sinking current; with L, F, C, G0, and G2-G5 programmed as low outputs and not driving a load; all outputs programmed low and not
driving a load; all inputs tied to V
register.
Note 4: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > V
have sink current to V
effective resistance to V
WARNING: Voltages in excess of 14 volts will cause damage to the pins. This warning excludes ESD transients.
Note 5: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 6: Parameter characterized but not tested.
C
= Instruction cycle time (Clock Input frequency divided by 10)
Crystal/Resonator, External
Internal R/C Oscillator
(Note 6)
Rise Time (Note 6)
Fall Time (Note 6)
t
t
t
SO, SK
All Others
Master Mode
Slave Mode
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
R/C Oscillator Frequency Variation
SETUP
HOLD
PD1
, t
PD0
specified)
Parameter
CC
CC
CC
c
when biased at voltages > V
and outputs driven low but not connected to a load.
)
UWH
is 750
UWS
) (Note 5)
) (Note 5)
CC
Figure 2-30 MICROWIRE/PLUS Timing
; clock monitor disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data
SK
SO
(typical). These two pins will not latch up. The voltage at the pins must be limited to < 14 Volts.
SI
UPD
t
)
UWS
4.5V
4.5V
4.5V
fr = Max
fr = 10 MHz Ext Clock
fr = 10 MHz Ext Clock
4.5V
4.5V
R
4.5V
4.5V
L
= 2.2k, C
CC
(the pins do not have source current when biased at a voltage below V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
Conditions
L
= 100 pF
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
t
UWH
COP8SAx7 MICROCONTROLLER
A
45
Min
200
1.0
DD
60
20
56
1
1
1
1
1
t
UPD
HALT is done with device neither sourcing
Typ
2.0
55
12
8
CC
TBD
Max
220
500
DC
0.7
1.0
and the pins will
1
%
ns
ns
CC
Units
MHz
kHz
). The
2-133
%
ns
ns
ns
ns
ns
t
t
t
t
c
c
c
c
s
s
s
s
s