COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 49

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

2.8
The architecture of the device is a modified Harvard architecture. With the Harvard
architecture, the program memory EPROM is separated from the data store memory
(RAM). Both EPROM and RAM have their own separate addressing space with separate
address buses. The architecture, though based on the Harvard architecture, permits
transfer of data from EPROM to RAM.
2.8.1
The CPU can do an 8-bit addition, subtraction, logical or shift operation in one
instruction (tc) cycle time.
There are six CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
B is an 8-bit RAM address pointer, which can be optionally post auto incremented or
decremented.
X is an 8-bit alternate RAM address pointer, which can be optionally post auto
incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/interrupt stack (in RAM).
With reset the SP is initialized to RAM address 02F Hex (devices with 64 bytes of RAM),
or initialized to RAM address 06F Hex (devices with 128 bytes of RAM).
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
FUNCTIONAL DESCRIPTION
CPU Registers
Figure 2-6 I/O Port Configurations–Input Mode
N
N
N
R
R
R
N
N
N
U
U
T
T
T
E
E
E
A
A
A
B
B
B
S
S
L
L
L
I
I
I
PORT L, G, AND C, F
PORT L, G, AND C, F
PORT L, G, AND C, F
Port read into a RAM address location
0 = Pullup disable
1 = Pullup enabled
0 = Input
CONFIGURATION
REGISTER
REGISTER
REGISTER
REGISTER
DATA
DATA
DATA
COP8SAx7 MICROCONTROLLER
V
CC
Weak
Pullup
(Software
Selectable)
2-11