COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 72

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

All interrupts force a branch to location 00FF Hex in program memory. The VIS
instruction may be used to vector to the appropriate service routine from location 00FF
Hex.
The Software trap has the highest priority while the default VIS has the lowest priority.
Each of the six maskable inputs has a fixed arbitration ranking and vector.
Figure 2-22 shows the Interrupt block diagram.
SOFTWARE TRAP
PENDING FLAG
TIMER T1
EXTERNAL
MULTI-INPUT WAKE UP
INTERRUPT
MICROWIRE/PLUS
FUTURE PERIPHERAL
IDLE TIMER
INTERRUPT ENABLE
GIE
Figure 2-22 Interrupt Block Diagram
2.13.2 Maskable Interrupts
All interrupts other than the Software Trap are maskable. Each maskable interrupt has
an associated enable bit and pending flag bit. The pending bit is set to 1 when the
interrupt condition occurs. The state of the interrupt enable bit, combined with the GIE
bit determines whether an active pending flag actually triggers an interrupt. All of the
maskable interrupt pending and enable bits are contained in mapped control registers,
and thus can be controlled by the software.
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COP8SAx7 MICROCONTROLLER