COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 54

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

External Reset
The RESET input when pulled low initializes the device. The RESET pin must be held
low for a minimum of one instruction cycle to guarantee a valid reset. During Power-Up
initialization, the user must ensure that the RESET pin is held low until the device is
within the specified V
(5x) greater than the power supply rise time or 15
recommended. Reset should also be wide enough to ensure crystal start-up upon Power-
Up.
RESET may also be used to cause an exit from the HALT mode.
With a slowly rising power supply, the device may start running before VCC is within the
guaranteed range. In this case, the user must provide an external RC network and a
diode shown in Figure 2-8.
2-16
RAM:
WATCHDOG (if enabled):
COP8SAx7 MICROCONTROLLER
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
UNAFFECTED after RESET with power already applied
RANDOM after RESET at power-on
The device comes out of reset with both the WATCHDOG logic and the Clock
Monitor detector armed, with the WATCHDOG service window bits set and
the Clock Monitor bit set. The WATCHDOG and Clock Monitor circuits are
inhibited during reset. The WATCHDOG service window bits being initial-
ized high default to the maximum WATCHDOG service window of 64k t
clock cycles. The Clock Monitor bit being initialized high will cause a Clock
Monitor error following reset if the clock has not reached the minimum spec-
ified frequency at the termination of reset. A Clock Monitor error will cause
an active low error output on pin G1. This error output will continue until 16
t
specified value, at which time the G1 output will go high.
C
–32 t
C
Figure 2-8 Reset Circuit Using External Reset
clock cycles following the clock frequency reaching the minimum
CC
voltage. An R/C circuit on the RESET pin with a delay 5 times
R/C > 5 x Power Supply Rise Time or
W
O
15
P
E
R
S
U
P
P
Y
L
s
, whichever is greater
R
C
D
V
RESET
GND
CC
COP8
sec whichever is greater, is
C