COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 198

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

The following table describes the instruction set of the NM93C06. In the table A3A2A1A0
corresponds to one of the sixteen 16-bit registers.
All commands and data are shifted in/out on the rising edge of the SK clock. All
instructions are initiated by a low-to-high transition on CS followed by a low-to-high
transition on DI.
A detailed explanation of the NMC93C06 E
considerations can be found in the data sheet. A source listing of the software used to
interface the NM93C06 with the COP8SAx7 is provided below.
4-6
COP8SAx7 APPLICATION IDEAS
3. The start bit on DI must be programmed as a “0” to “1” transition following a
4. In the read mode, following an instruction and data train, the DI is a “don’t
5. The data out train starts with a dummy bit 0 and is terminated by chip dese-
6. After a read cycle, the CS must be brought low for one SK clock cycle before
Commands Start Bit Opcode
READ
WRITE
ERASE
EWEN
EWDS
WRAL
ERAL
30 ms maximum. It should be set at the typical or minimum specification of
10 ms.
CS enable (“0” to “1”) when executing any instruction. One CS enable transi-
tion can execute only one instruction.
care” while the data is being output for the next 17 bits or clocks. The same
is true for other instructions after the instruction and data have been fed in.
lect. Any extra SK cycle after 16 bits is ignored. If CS is held on after all 16 of
the data bits have been output, the DO will output the state of DI until an-
other CS low to high transition starts a new instruction cycle.
another instruction cycle starts.
1
1
1
1
1
1
1
0000
1000
0100
1100
1100
1100
1100
2
A3A2A1A0 Read Register 0–15
A3A2A1A0 Write Register 0–15
A3A2A1A0 Erase Register 0–15
0001
0010
0100
0101
PROM timing, instruction set, and other
Address
Write/Erase Enable
Write/Erase Disable
Write All Registers
Erase All Registers
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