COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 215

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

is applied to the system, SW1 closes and the device exits the HALT mode via a Multi-Input
Wakeup pin. The MIWU pin is then reconfigured as an output to power up the sensor
circuit, thus power remains on for a programmed period of time even when the switch is
open again. The measurement and display are then performed. After completing the
measurement and display routines, the COP8SAx7 reconfigures the sensor power pin as a
Wakeup pin, thereby disconnecting power from the sensor circuit. The device then re-
enters the HALT mode.
The 16-bit timer can be used to generate the interrupts required to refresh the LCD
display. An internal power-on reset circuit is used in this application.
4.8
Zero cross detection is often used in appliances connected to the AC power line. The line
frequency is a useful time base for applications such as industrial timers or irons which
switch off if not used for five minutes. Phase-controlled applications require a consistent
timing reference in phase with the line voltage.
The COP8SAx7 requires a square wave, magnitude V
power line voltage, connected to a input port pin for a simple time base. For a phase-control
time base, this waveform should preferably be in phase with the line voltage, although
control is still possible if there is a predictable, constant phase lag, less than the phase lag
introduced by the load. The choice of zero cross detection circuit depends on factors such as
cost, the type of power supply used in the appliance, and the expected interference.
The zero cross detection input can either be polled by software or can be connected to the
G0 interrupt line. Polling the pin by software is the simplest technique and saves the
interrupt for another function, but has the disadvantage that the polling procedure can be
interrupted, causing inaccuracies in synchronization. Disabling the interrupt during the
polling is not always possible, as the interrupt may be required for the implementation of
other features.
Connecting the zero cross detection input to the external interrupt pin guarantees
synchronization. It has the additional advantage that a regular interrupt is generated,
which could interrupt the processor out of a fault condition. The interrupt routine only
needs to test the integrity of the stack to determine whether such a fault has occurred.
The following software example shows how software polling of the zero cross line is
implemented.
ZCD:
WHILO:
WLOHI:
RSYNC:
ENDZCD:
ZERO CROSS DETECTION
LD
IFBIT
JP
IFBIT
JP
SBIT
JP
IFBIT
JP
JP
RBIT
B,#STATUS
SYNCHRO,[B]
WLOHI
3,PORTLP
WHILO
SYNCHRO,[B]
ENDZCD
3,PORTLP
RSYNC
WLOHI
SYNCHRO,[B]
;Save bytes using the B pointer
;If SYNCHRO is 1, wait for a rising edge
;otherwise wait for a falling edge.
;Wait for falling edge
;SYNCHRO = 1, so wait for rising edge
;next time.
;Wait for a rising edge
;SYNCHRO = 0, so wait for a falling edge
;next time.
;End of example
COP8SAx7 APPLICATION IDEAS
CC
, at the same frequency as the
4-23