COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 75

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

Hex, then the vector location 0yFE and -0yFF should contain the data 03 and 10 Hex,
respectively. When a Software Trap interrupt occurs and the VIS instruction is executed,
the program jumps to the address specified in the vector table.
The interrupt sources in the vector table are listed in order of rank, from highest to
lowest priority. If two or more enabled and pending interrupts are detected at the same
time, the one with the highest priority is serviced first. Upon return from the interrupt
service routine, the next highest-level pending interrupt is serviced.
If the VIS instruction is executed, but no interrupts are enabled and pending, the lowest-
priority interrupt vector is used, and a jump is made to the corresponding address in the
vector table. This is an unusual occurrence, and probably the result of an error. It can
result from a change in the enable bits or pending flags prior to using the VIS instruction,
or from inadvertent execution of the VIS command outside of the context of an interrupt.
It is a good idea to make this vector point to the Software Trap interrupt service routine
or some other error handling routine. A normal RETI instruction should not be used in
any such routine because the stack might not contain a valid return address
(1) Highest
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16) Lowest
ARBITRATION
*y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte
block except if VIS is located at the last address of a block. In this case, the table must be in the next block.
RANKING
Software
Reserved
External
Timer T0
Timer T1
Timer T1
MICROWIRE/PLUS
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Port L/Wakeup
Default
SOURCE
INTR Instruction
Future
G0
Underflow
T1A/Underflow
T1B
Busy Low
Future
Future
Future
Future
Future
Future
Future
Port L Edge
VIS Instruction
Execution without any inter-
rupts
DESCRIPTION
COP8SAx7 MICROCONTROLLER
0yFE - 0yFF
0yFC - 0yFD
0yFA - 0yFB
0yF8 - 0yF9
0yF6 - 0yF7
0yF4 - 0yF5
0yF2 - 0yF3
0yF0 - 0yF1
0yEE - 0yEF
0yEC - 0yED
0yEA - 0yEB
0yE8 - 0yE9
0yE6 - 0yE7
0yE4 - 0yE5
0yE2 - 0yE3
0yE0 - 0yE1
(Hi-Low Byte)
ADDRESS
VECTOR*
2-37