COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 68

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

with a Multi-Input Wakeup from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the twelfth bit (representing 4.096 ms at
internal clock frequency of 10 MHz, t
This toggle condition of the twelfth bit of the IDLE Timer T0 is latched into the T0PND
pending flag.
The user has the option of being interrupted with a transition on the twelfth bit of the
IDLE Timer T0. The interrupt can be enabled or disabled via the T0EN control bit.
Setting the T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case,
when the T0PND bit gets set, the device will first execute the Timer T0 interrupt service
routine and then return to the instruction following the “Enter Idle Mode” instruction.
Alternatively, the user can enter the IDLE mode with the IDLE Timer T0 interrupt
disabled. In this case, the device will resume normal operation with the instruction
immediately following the “Enter IDLE Mode” instruction.
NOTE:
2-30
DEVICE ACTIVE
COP8SAx7 MICROCONTROLLER
. . .
SBIT 6, PORTGD
NOP
NOP
IDLE TIMER
CONTENTS
OSC:
It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions are
necessary to allow clock resynchronization following the HALT or IDLE
modes.
Figure 2-19 Wakeup From IDLE
CLK-MON.t
Active:
T0
DEVICE IN IDLE MODE
C
= 1 s) of the IDLE Timer toggles.
RAM Reg’s
Unaltered:
DELAY
Registers
Function
Timers
Ports
RAM
Timer
bit 12
Idle
PORT L RESET
(out of IDLE Mode)
DEVICE ACTIVE