COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 73

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

An interrupt is triggered only when all of these conditions are met at the beginning of an
instruction. If different maskable interrupts meet these conditions simultaneously, the
highest-priority interrupt will be serviced first, and the other pending interrupts must
wait.
Upon Reset, all pending bits, individual enable bits, and the GIE bit are reset to zero.
Thus, a maskable interrupt condition cannot trigger an interrupt until the program
enables it by setting both the GIE bit and the individual enable bit. When enabling an
interrupt, the user should consider whether or not a previously activated (set) pending
bit should be acknowledged. If, at the time an interrupt is enabled, any previous
occurrences of the interrupt should be ignored, the associated pending bit must be reset
to zero prior to enabling the interrupt. Otherwise, the interrupt may be simply enabled;
if the pending bit is already set, it will immediately trigger an interrupt. A maskable
interrupt is active if its associated enable and pending bits are set.
An interrupt is an asynchronous event which may occur before, during, or after an
instruction cycle. Any interrupt which occurs during the execution of an instruction is not
acknowledged until the start of the next normally executed instruction is to be skipped,
the skip is performed before the pending interrupt is acknowledged.
At the start of interrupt acknowledgment, the following actions occur:
The device requires seven instruction cycles to perform the actions listed above.
If the user wishes to allow nested interrupts, the interrupts service routine may set the
GIE bit to 1 by writing to the PSW register, and thus allow other maskable interrupts to
interrupt the current service routine. If nested interrupts are allowed, caution must be
exercised. The user must write the program in such a was as to prevent stack overflow,
loss of saved context information, and other unwanted conditions.
The interrupt service routine stored at location 00FF Hex should use the VIS instruction
to determine the cause of the interrupt, and jump to the interrupt handling routine
corresponding to the highest priority enabled and active interrupt. Alternately, the user
may choose to poll all interrupt pending and enable bits to determine the source(s) of the
1. The enable bit associated with that interrupt is set.
2. The GIE bit is set.
3. The device is not processing a non-maskable interrupt. (If a non-maskable in-
1. The GIE bit is automatically reset to zero, preventing any subsequent
2. The address of the instruction about to be executed is pushed onto the stack.
3. The program counter(PC) is loaded with 00FF Hex, causing a jump to that
terrupt is being serviced, a maskable interrupt must wait until that service
routine is completed.)
maskable interrupt from interrupting the current service routine.This fea-
ture prevents one maskable interrupt from interrupting another one being
serviced.
program memory location.
COP8SAx7 MICROCONTROLLER
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