COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 86

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

use the MICROWIRE/PLUS, the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits, SL0 and SL1, in the CNTRL
register. Table 2-9 details the different clock rates that may be selected.
2.15.1 MICROWIRE/PLUS Operation
Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to start
shifting the data. It gets reset when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If enabled, an interrupt is
generated when eight data bits have been shifted. The device may enter the
MICROWIRE/PLUS mode either as a Master or as a Slave. Figure 2-25 shows how two
microcontroller devices and several peripherals may be interconnected using the
MICROWIRE/PLUS arrangements.
The SIO register should only be loaded when the SK clock is in the idle phase. Loading
the SIO register while the SK clock is in the active phase, will result in undefined data
in the SIO register.
Setting the BUSY flag when the input SK clock is in the active phase while in the MI-
CROWIRE/PLUS is in the slave mode may cause the current SK clock for the SIO shift
register to be narrow. For safety, the BUSY flag should only be set when the input SK
clock is in the idle phase.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the shift clock (SK) is generated
internally. The MICROWIRE Master always initiates all data exchanges. The MSEL bit
in the CNTRL register must be set to enable the SO and SK functions onto the G Port.
The SO and SK pins must also be selected as outputs by setting appropriate bits in the
Port G configuration register. In the slave mode, the shift clock stops after 8 clock pulses.
Table 2-10 summarizes the bit settings required for Master mode of operation.
2-48
COP8SAx7 MICROCONTROLLER
Table 2-9 MICROWIRE/PLUS Master Mode Clock Select
Where t
SL1
0
0
1
c
is the instruction cycle clock
WARNING
SL0
0
1
x
SK period
2 X t
4 X t
8 X t
c
c
c