COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 64

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

cannot determine the timer value when the external event occurs. The capture register
eliminates the latency time, thereby allowing the applications program to retrieve the
timer value stored in the capture register.
In this mode, the timer T1 is constantly running at the fixed tc rate. The two registers,
R1A and R1B, act as capture registers. Each register acts in conjunction with a pin. The
register R1A acts in conjunction with the T1A pin and the register R1B acts in
conjunction with the T1B pin.
The timer value gets copied over into the register when a trigger event occurs on its
corresponding pin. Control bits, T1C3, T1C2 and T1C1, allow the trigger events to be
specified either as a positive or a negative edge. The trigger condition for each input pin
can be specified independently.
The trigger conditions can also be programmed to generate interrupts. The occurrence of
the specified trigger condition on the T1A and T1B pins will be respectively latched into
the pending flags, T1PNDA and T1PNDB. The control flag T1ENA allows the interrupt
on T1A to be either enabled or disabled. Setting the T1ENA flag enables interrupts to be
generated when the selected trigger condition occurs on the T1A pin. Similarly, the flag
T1ENB controls the interrupts from the T1B pin.
Underflows from the timer can also be programmed to generate interrupts. Underflows
are latched into the timer T1C0 pending flag (the T1C0 control bit serves as the timer
underflow interrupt pending flag in the Input Capture mode). Consequently, the T1C0
control bit should be reset when entering the Input Capture mode. The timer underflow
interrupt is enabled with the T1ENA control flag. When a T1A interrupt occurs in the
Input Capture mode, the user must check both the T1PNDA and T1C0 pending flags in
order to determine whether a T1A input capture or a timer underflow (or both) caused
the interrupt.
Figure 2-17 shows a block diagram of the timer in Input Capture mode.
2-26
COP8SAx7 MICROCONTROLLER
Figure 2-17 Timer in Input Capture Mode
INPUTCAPTURE
INPUTCAPTURE
16 BIT TIMER/
REGISTER
COUNTER
REGISTER
R1A
R1B
EDGE SELECTOR
LOGIC
T1A
INTERRUPT
T1B
INTERRUPT
T1A
T1B