COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 76

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

the source of an interrupt. Although it is possible to poll the pending bits to detect the
source of an interrupt, this practice is not recommended. The use of polling allows the
standard arbitration ranking to be altered, but the reliability of the interrupt system is
compromised. The polling routine must individually test the enable and pending bits of
each maskable interrupt. If a Software Trap interrupt should occur, it will be serviced
last, even though it should have the highest priority. Under certain conditions, a
Software Trap could be triggered but not serviced, resulting in an inadvertent “locking
out” of all maskable interrupts by the Software Trap pending flag. Problems such as this
can be avoided by using VIS instruction.
VIS Execution
When the VIS instruction is executed it activates the arbitration logic. The arbitration
logic generates an even number between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at the time of the 1st cycle of
VIS is executed. For example, if the software trap interrupt is active, FE is generated. If
the external interrupt is active and the software trap interrupt is not, then FA is
generated and so forth. If the only active interrupt is software trap, than E0 is generated.
This number replaces the lower byte of the PC. The upper byte of the PC remains
unchanged. The new PC is therefore pointing to the vector of the active interrupt with
the highest arbitration ranking. This vector is read from program memory and placed
into the PC which is now pointed to the 1st instruction of the service routine of the active
interrupt with the highest arbitration ranking.
Figure 2-23 illustrates the different steps performed by the VIS instruction. Figure 2-24
shows a flowchart for the VIS instruction.
2-38
COP8SAx7 MICROCONTROLLER
PC
PC
(generates an even number
ABRITRATION LOGIC
STARTING ADDRESS
HIGH
between E0 and FE)
after an interrupt
INTERRUPT
BIT 7:0
VIS
Figure 2-23 VIS Operation
LOW
0FF
INTERRUPT SERVICE
PROGRAM MEMORY
STARTING
ADDRESS
ROUTINE
VIS
Interrupt
HIGH
LOW
Vector
Table
Vector table is
256 byte page
same as PC