COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 254

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

Reset 2-15
Reset Carry (RC) 2-98
Reset Memory Bit (RBIT) 2-97
Reset Pending (RPND) 2-103
Return and Skip (RETSK) 2-101
Return from Interrupt (RETI) 2-100
Return from Subroutine (RET) 2-99
RF transmission and digital security code generation/
ROM, defined 1-1
Rotate Accumulator Left Through Carry (RLC) 2-102
Rotate Accumulator Right Through Carry (RRC) 2-104
Routines/subroutines 1-20
Rudimentary D-A converter 4-10
Set Carry (SC) 2-106
Set Memory Bit (SBIT) 2-105
Silicon design changes to achieve low EMI 2-141
Single slope A/D or V/F conversion 4-42
SK idle polarity 2-49
SK phase operation 2-49
Slave mode 2-49
Small LED 4-42
Small transmitter size 4-27
Software Trap 2-41
SP register 2-11
Stack Control instructions 2-61
Stack manipulation 1-20
Stacks 1-11
Status register 1-12
Subtract with Carry (SUBC) 2-107
Swap Nibbles of Accumulator (SWAP) 2-108
Symbol definition 2-113
T1C0 2-27
T1C1 2-27
T1C2 2-27
T1C3 2-27
T1ENA 2-27
T1ENB 2-27
T1PNDA 2-27
T1PNDB 2-27
Temperature detection 4-47
Temperature ranges 2-3
Test Bit (IFBIT) 2-72
Test if Carry (IFC) 2-74
Test if Equal (IFEQ) 2-75
Test if Greater Than (IFGT) 2-76
Test If No Carry (IFNC) 2-77
Test If Not Equal (IFNE) 2-78
Testing a remote normally open swtich for connection 4-2
Time keeping 4-37
Timer capture example 4-13
4
PSW 2-22
SP 2-11
status 1-12
X 2-11
external 2-16
on-chip power-on 2-17
transmission 4-34
INDEX
S
T
Timer Control Flags 2-27
Timer PWM applications 4-10
Timer T0 2-23
Timer T1 2-23
Timers 2-23
Timing 1-15
Timing signal 1-1
Tone dialing 4-33
Transfer-of Control instructions 2-60
Transfer-of-Control addressing mode 2-57
Triac control 4-17
Under-voltage detection 4-48
User storage space in EPROM 2-13
Vector Interrupt Select (VIS) 2-109
Vector table 2-37
VIS instruction 2-36
Von Neumann architecture 1-6
WATCHDOG 2-43, 2-44
WorldWide Web 3-11
X Indirect addressing mode 2-55
X Indirect with Post-Incrementing/Decrementing ad-
X register 2-11
Zero cross detection 4-23, 4-43
applications 4-10
IDLE 2-23
T0 2-23
T1 2-23
execution 2-38
dressing mode 2-56
W
U
V
X
Z