COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 67

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

stabilized before allowing instruction execution. In this case, upon detecting a valid
Wakeup signal, only the oscillator circuitry is enabled. The IDLE timer is loaded with a
value of 256 and is clocked with the tc instruction cycle clock. The tc clock is derived by
dividing the oscillator clock down by a factor of 10. The Schmitt trigger following the CKI
inverter on the chip ensures that the IDLE timer is clocked only when the oscillator has
a sufficiently large amplitude to meet the Schmitt trigger specifications. This Schmitt
trigger is not part of the oscillator closed loop. The start-up time-out from the IDLE timer
enables the clock signals to be routed to the rest of the chip.
OSC:
256 t
C
DEVICE IN HALT MODE
DEVICE ACTIVE
DEVICE ACTIVE
Unaltered:
RAM Reg’s
Function
Registers
Timers
Ports
Active:
PORT L
RESET
CKO (G7)
RAM
CLK-MON.
Figure 2-18 Wakeup From HALT
If an R/C clock option is being used, the fixed delay is introduced optionally. A control bit,
CLKDLY, mapped as configuration bit G7, controls whether the delay is to be introduced
or not. The delay is included if CLKDLY is set, and excluded if CLKDLY is reset. The
CLKDLY bit is cleared on reset.
The device has two options associated with the HALT mode. The first option enables the
HALT mode feature, while the second option disables the HALT mode selected through
bit 0 of the ECON register. With the HALT mode enable option, the device will enter and
exit the HALT mode as described above. With the HALT disable option, the device cannot
be placed in the HALT mode (writing a “1” to the HALT flag will have no effect, the HALT
flag will remain “0”).
The WATCHDOG detector circuit is inhibited during the HALT mode. However, the clock
monitor circuit if enabled remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT mode as a result of a runaway
program or power glitch.
If the device is placed in the HALT mode, with the R/C oscillator selected, the clock input
pin (CKI) is forced to a logic high internally. With the crystal or external oscillator the
CKI pin is TRI-STATE.
2.11.2 IDLE Mode
The device is placed in the IDLE mode by writing a “1” to the IDLE flag (G6 data bit). In
this mode, all activities, except the associated on-board oscillator circuitry and the IDLE
Timer T0, are stopped.
COP8SAx7 MICROCONTROLLER
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