COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 74

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

interrupt. If more than one interrupt is active, the user’s program must decide which
interrupt to service.
Within a specific interrupt service routine, the associated pending bit should be cleared.
This is typically done as early as possible in the service routine in order to avoid missing
the next occurrence of the same type of interrupt event. Thus, if the same event occurs a
second time, even while the first occurrence is still being serviced, the second occurrence
will be serviced immediately upon return from the current interrupt routine.
An interrupt service routine typically ends with an RETI instruction. This instruction set
the GIE bit back to 1, pops the address stored on the stack, and restores that address to
the program counter. Program execution then proceeds with the next instruction that
would have been executed had there been no interrupt. If there are any valid interrupts
pending, the highest-priority interrupt is serviced immediately upon return from the
previous interrupt.
2.13.3 VIS Instruction
The general interrupt service routine, which starts at address 00FF Hex, must be
capable of handling all types of interrupts. The VIS instruction, together with an
interrupt vector table, directs the device to the specific interrupt handling routine based
on the cause of the interrupt.
VIS is a single-byte instruction, typically used at the very beginning of the general
interrupt service routine at address 00FF Hex, or shortly after that point, just after the
code used for context switching. The VIS instruction determines which enabled and
pending interrupt has the highest priority, and causes an indirect jump to the address
corresponding to that interrupt source. The jump addresses (vectors) for all possible
interrupts sources are stored in a vector table.
The vector table may be as long as 32 bytes (maximum of 16 vectors) and resides at the
top of the 256-byte block containing the VIS instruction. However, if the VIS instruction
is at the very top of a 256-byte block (such as at 00FF Hex), the vector table resides at
the top of the next 256-byte block. Thus, if the VIS instruction is located somewhere
between 00FF and 01DF Hex (the usual case), the vector table is located between
addresses 01E0 and 01FF Hex. If the VIS instruction is located between 01FF and 02DF
Hex, then the vector table is located between addresses 02E0 and 02FF Hex, and so on.
Each vector is 15 bits long and points to the beginning of a specific interrupt service
routine somewhere in the 32-Kbyte memory space. Each vector occupies two bytes of the
vector table, with the higher-order byte at the lower address. The vectors are arranged
in order of interrupt priority. The vector of the maskable interrupt with the lowest rank
is located to 0yE0 (higher-order byte) and 0yE1 (lower-order byte). The next priority
interrupt is located at 0yE2 and 0yE3, and so forth in increasing rank. The Software Trap
has the highest rand and its vector is always located at 0yFE and 0yFF. The number of
interrupts which can become active defines the size of the table.
Table 2-5 shows the types of interrupts, the interrupt arbitration ranking, and the
locations of the corresponding vectors in the vector table.
The vector table should be filled by the user with the memory locations of the specific
interrupt service routines. For example, if the Software Trap routine is located at 0310
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COP8SAx7 MICROCONTROLLER