COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 92

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

2.17.1 Introduction
This section defines the instruction set of the COPSAx7 Family members. It contains
information about the instruction set features, addressing modes and types.
2.17.2 Instruction Features
The strength of the instruction set is based on the following features:
2.17.3 Addressing Modes
The instruction set offers a variety of methods for specifying memory addresses. Each
method is called an addressing mode. These modes are classified into two categories:
operand addressing modes and transfer-of-control addressing modes. Operand
addressing modes are the various methods of specifying an address for accessing (reading
or writing) data. Transfer-of-control addressing modes are used in conjunction with jump
instructions to control the execution sequence of the software program.
Operand Addressing Modes
The operand of an instruction specifies what memory location is to be affected by that
instruction. Several different operand addressing modes are available, allowing memory
locations to be specified in a variety of ways. An instruction can specify an address
directly by supplying the specific address, or indirectly by specifying a register pointer.
The contents of the register (or in some cases, two registers) point to the desired memory
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• Mostly single-byte opcode instructions minimize program size.
• One instruction cycle for the majority of single-byte instructions to minimize pro-
• Many single-byte, multiple function instructions such as DRSZ.
• Three memory mapped pointers: two for register indirect addressing, and one for
• Sixteen memory mapped registers that allow an optimized implementation of cer-
• Ability to set, reset, and test any individual bit in data memory address space, in-
• Register-Indirect LOAD and EXCHANGE instructions with optional automatic
• Unique instructions to optimize program size and throughput efficiency. Some of
gram execution time.
the software stack.
tain instructions.
cluding the memory-mapped I/O ports and registers.
post-incrementing or decrementing of the register pointer. This allows for greater
efficiency (both in cycle time and program code) in loading, walking across and pro-
cessing fields in data memory.
these instructions are: DRSZ, IFBNE, DCOR, RETSK, VIS and RRC.
COP8SAx7 MICROCONTROLLER