COP8SA-DM National Semiconductor, COP8SA-DM Datasheet - Page 71

• Manufacturer Part Number: COP8SA-DM
• Description: MODULE DEBUGGING FOR COP8SA
• Manufacturer: National Semiconductor

Specifications of COP8SA-DM

• Module/board Type: Debugger Module
• For Use With/related Products: Cop 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *COP8SA-DM

either a positive edge (low to high transition) or a negative edge (high to low transition).
This selection is made via the register WKEDG, which is an 8-bit control register with a
bit assigned to each L Port pin. Setting the control bit will select the trigger condition to
be a negative edge on that particular L Port pin. Resetting the bit selects the trigger
condition to be a positive edge. Changing an edge select entails several steps in order to
avoid a Wakeup condition as a result of the edge change. First, the associated WKEN bit
should be reset, followed by the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose we wish to change the edge
select from positive (low going high) to negative (high going low) for L Port bit 5, where
bit 5 has previously been enabled for an input interrupt. The program would be as
follows:
If the L port bits have been used as outputs and then changed to inputs with Multi-Input
Wakeup/Interrupt, a safety procedure should also be followed to avoid wakeup
conditions. After the selected L port bits have been changed from output to input but
before the associated WKEN bits are enabled, the associated edge select bits in WKEDG
should be set or reset for the desired edge selects, followed by the associated WKPND bits
being cleared.
This same procedure should be used following reset, since the L port inputs are left
floating as a result of reset.
The occurrence of the selected trigger condition for Multi-Input Wakeup is latched into a
pending register called WKPND. The respective bits of the WKPND register will be set
on the occurrence of the selected trigger edge on the corresponding Port L pin. The user
has the responsibility of clearing these pending flags. Since WKPND is a pending register
for the occurrence of selected wakeup conditions, the device will not enter the HALT
mode if any Wakeup bit is both enabled and pending. Consequently, the user must clear
the pending flags before attempting to enter the HALT mode.
WKEN and WKEDG are all read/write registers, and are cleared at reset. WKPND
register contains random value after reset.
2.13 INTERRUPTS
2.13.1 Introduction
The device supports eight vectored interrupts. Interrupt sources include Timer 1, Timer
T0, Port L Wakeup, Software Trap, MICROWIRE/PLUS, and External Input.
RBIT 5, WKEN; Disable MIWU
SBIT 5, WKEDG; Change edge polarity
RBIT 5, WKPND; Reset pending flag
SBIT 5, WKEN; Enable MIWU
COP8SAx7 MICROCONTROLLER
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