Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 130

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 64. Timer 0–2 Noise Filter Control Register (TxNFC)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Timer 0–2 Noise Filter Control Register
NFEN
R/W
7
0
PWMxEO—PWM x Event Overrun
This bit indicates that an overrun error has occurred. An overrun occurs when 
a new capture/compare event occurs before the previous PWMxEF bit is cleared. 
Clearing the associated PWMxEF bit in the TxSTAT register clears this bit. 
0 = No Overrun
1 = Capture/Compare Event Flag Overrun
RTOEF—Reload Timeout Event Flag
This flag is set if timer counts up to the reload value and is reset to
Software can use this bit to determine if a reload occurred prior to a capture. 
It can also determine if timer interrupt is due to a reload event. 
0 = No Reload Timeout event occurred
1 = A Reload Timeout event occurred
Reserved—Must be 0
PWMxEF—PWM x Event Flag
This bit indicates if a capture/compare event occurred for this PWM channel. 
Software can use this bit to determine the PWM channel responsible for generating the
timer interrupt. This event flag is cleared by writing a 1 to the bit. These bits will 
be set when an event occurs independent of the setting of the timer interrupt 
enable bit.
0 = No Capture/Compare Event occurred for this PWM channel
1 = A Capture/Compare Event occurred for this PWM channel
The Timer 0–2 Noise Filter Control Register (TxNFC) enable/disable Timer Noise 
Filter and set the noise filter control.
NFEN—Noise Filter Enable
0 = Noise Filter is disabled. 
1 = Noise Filter is enabled. Receive data is preprocessed by the noise filter.
6
0
NFCTL
R/W
5
0
P R E L I M I N A R Y
F2CH, F2DH, F2EH
4
0
3
0
Z8 Encore! XP
2
0
Reserved
Product Specification
R
0001H
1
0
®
. 
F1680 Series
0
0
Timers
116