Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 237

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Note:
7. The I
8. After one bit of the address has been shifted out by the SDA signal, the transmit
9. The software responds by writing the transmit data into the I
10. The I
11. The I
12. The I
13. The I
14. If more bytes remain to be sent, return to
15. When there is no more data to be sent, the software responds by setting the
16. If no additional transaction is queued by the master, the software can clear the
17. The I
18. The I
If the slave terminates the transaction early by responding with a Not Acknowledge during
the transfer, the I
minate the transaction by setting either the
(end this transaction, start a new one). In this case, it is not necessary for software to set
the
transmitted. The I
acknowledge case.
Master Write Transaction with a 10-Bit Address
Figure 44
FLUSH
Register.
interrupt asserts.
SDA signal.
the next high period of SCL. The I
I
If the slave does not acknowledge the address byte, the I
bit in the I
Register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends a
transaction is complete, and the following steps can be ignored.
I
sent, the transmit interrupt asserts.
the I
of the I
2
2
C Status Register.
C Data Register.
2
2
2
2
2
2
2
2
C Control Register (or the
displays the data transfer format from a Master to a 10-bit addressed slave.
C controller loads the I
C controller shifts the remainder of the address and the Write bit out via the
C slave sends an Acknowledge (by pulling the SDA signal Low) during 
C controller loads the contents of the I
C controller shifts the data out via the SDA signal. After the first bit is 
C controller completes transmission of the data on the SDA signal.
C controller sends a
bit of the I2CCTL Register to flush the data that was previously written but not
2
STOP
C Control Register.
2
C Status Register, sets the
2
2
C controller asserts the
condition on the bus, and clears the
C controller hardware automatically flushes transmit data in the not
TXI
P R E L I M I N A R Y
bit. The I
STOP
2
C Shift Register with the contents of the I
START
condition to the I
2
2
C controller flushes the Transmit Data Register,
C controller sets the ACK bit in the 
ACKV
NCKI
STOP
bit to initiate a new transaction).
Step
interrupt and halts. The software must ter-
bit, and clears the
2
C Shift Register with the contents of the
bit (end transaction) or the
9.
STOP
2
C bus.
Z8 Encore! XP
and
2
C controller sets the NCKI
Product Specification
NCKI
2
I2C Master/Slave Controller
C Data Register.
ACK
bits. The 
bit in the I
®
F1680 Series
2
C Data
START
STOP
2
C State
TXI
STOP
bit of
bit
bit
223