Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 201

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 105. Sample Settling Time (ADCSST)
PS025011-1010
Table 106. Sample Time (ADCST)
BITS
FIELD
RESET
R/W
ADDR
Bit Position
[7:4]
[3:0]
SST
Bit Position Value (H)
[7:6]
[5:0]
ST
BITS
FIELD
RESET
R/W
ADDR
Sample Settling Time Register
Sample Time Register
0
00-3F
7
7
The Sample Settling Time Register
from the SAMPLE/HOLD signal to the START signal, when the conversion can begin.
The number of clock cycles required for settling will vary from system to system
depending on the system clock period used. The system designer should program this
register to contain the number of clocks required to meet a 0.5 µs minimum settling time.
Value (H)
0h
0h-Fh
The Sample Time Register
sample after a conversion begins by setting the START bit in the ADC Control Register or
initiated by the PWM. The number of system clock cycles required for sample time varies
from system to system, depending on the clock period used. The system designer should
program this register to contain the number of system clocks required to meet a 1.8 µs
minimum sample time.
Reserved
R/W
0
Description
Reserved—Must be 0.
Sample Hold time in number of system clock periods to meet 1.8 µs minimum.
6
6
Description
Sample settling time in number of system clock periods to meet 0.5 µs
minimum.
Reserved—Must be 0.
Reserved
R
0
5
5
1
(Table
P R E L I M I N A R Y
106) is used to program the length of active time for the
4
4
1
(Table 105)
F74H
F75H
3
1
3
1
is used to program the length of time 
R/W
ST
Z8 Encore! XP
2
1
2
1
SST
R/W
Product Specification
Analog-to-Digital Converter
1
1
1
1
®
F1680 Series
0
1
0
1
187