Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 245
Z8F2480AN020SG
Manufacturer Part Number
Z8F2480AN020SG
Description
MCU 8BIT 24KB FLASH 44LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F2480AN020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
37
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
44-LQFP
Processor Series
Z8F248x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
37
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 8 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4676
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z8F2480AN020SG
Manufacturer:
Zilog
Quantity:
85
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- Download datasheet (19Mb)
s
PS025011-1010
S
Slave Address
1st Byte
4. The Master detects the Acknowledge and sends the byte of data.
5. The I
6. The software responds by reading the I2CISTAT Register, finding the
7. The master and slave loops through
8. The master sends the
Slave Receive Transaction with 10-Bit Address
The data transfer format for writing data from a master to a slave with 10-bit addressing
is displayed in
Controller operating as a slave in 10-bit addressing mode and receiving data from the bus
master.
Figure 48. Data Transfer Format—Slave Receive Transaction with 10-Bit Address
1. The software configures the controller for operation as a slave in 10-bit addressing
If software is only able to accept a single byte, it sets the
Register at this time.
Acknowledge depending on the state of the
controller generates the receive data interrupt by setting the
Register.
and reading the I2CDATA Register clearing the
one more data byte it sets the
Acknowledge instruction or runs out of data to send.
cause the I
Register). Because the slave received data from the master, the software takes no
action in response to the STOP interrupt other than reading the I2CISTAT Register to
clear the
mode, as follows:
(a) Initialize the
(b) Optionally set the
(c) Initialize the
(d) Set
mode or MASTER/SLAVE mode with 10-bit addressing.
bits in the I2CMODE Register.
2
W=0
C controller receives the data byte and responds with Acknowledge or Not
IEN
STOP
2
Figure
C controller to assert a STOP interrupt (the
= 1 in the I2CCTL Register. Set
bit in the I2CISTAT Register.
A
MODE
SLA[7:0]
48. The procedure that follows describes the I
Slave Address
STOP
GCE
field in the I2CMODE Register for either SLAVE ONLY
2nd Byte
P R E L I M I N A R Y
bit.
or
bits in the I2CSLVAD Register and the
NAK
RESTART
bit in the I2CCTL Register.
Step 4
A
signal on the bus. Either of these signals can
to
NAK
NAK
Data
Step 6
RDRF
bit in the I2CCTL Register. The I
= 0 in the I
Z8 Encore! XP
until the master detects a Not
bit. If software can accept only
A
STOP
NAK
RDRF
Product Specification
2
I2C Master/Slave Controller
bit = 1 in the I2CISTAT
Data
bit in the I2CCTL
C Control Register.
2
C Master/Slave
bit in the I2CISTAT
SLA[9:8]
®
RDRF
A/A
F1680 Series
bit = 1
P/S
2
C
231
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