Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 315

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 165. OCD Status Register (OCDSTAT)
PS025011-1010
BITS
FIELD
RESET
R/W
OCD Status Register
IDLE
0 = OCDCNTR is setup as counter
1 = OCDCNTR generates hardware break when PC == OCDCNTR
BRKZRO—Break when OCDCNTR ==
If this bit is set, then the OCD automatically sets the DBGMODE bit when the 
OCDCNTR register counts down to
is not reset when the part leaves DEBUG Mode.
0 = OCD does not generate BRK when OCDCNTR decrements to
1 = OCD sets DBGMODE to 1 when OCDCNTR decrements to
Reserved—Must be 0
RST—Reset
Setting this bit to 1 resets the device. The controller goes through a normal POR 
sequence with the exception that the On-Chip Debugger is not reset. This bit is 
automatically cleared to 0 when the reset finishes. 
0 = No effect.
1 = Reset the device.
The OCD Status register
the debugger and the system.
IDLE—CPU idle
This bit is set if the part is in Debug mode (DBGMODE is 1) or if a BRK instruction has
occurred since the last time OCDCTL was written. This can be used to determine if the
CPU is running or if it is idle.
0 = The eZ8 CPU is running.
1 = The eZ8 CPU is either stopped or looping on a BRK instruction.
HALT—HALT Mode
0 = The device is not in HALT mode.
1 = The device is in HALT mode.
RPEN—Read Protect Option Bit Enabled
0 = The Read Protect Option Bit is disabled (Flash option bit is 1).
1 = The Read Protect Option Bit is enabled (Flash option bit is 0), disabling 
Reserved—Must be 0
R
7
0
many OCD commands.
HALT
R
6
0
RPEN
R
5
0
(Table
P R E L I M I N A R Y
165) reports status information about the current state of
4
0000H
. If this bit is set, the OCDCNTR register 
0000H
3
Reserved
Z8 Encore! XP
R
2
0
Product Specification
0000H
0000H
1
®
On-Chip Debugger
F1680 Series
0
301