Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 89

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 35. Interrupt Request 0 Register (IRQ0)
Interrupt Control Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
Caution:
Caution:
Software Interrupt Assertion
Interrupt Request 0 Register
R/W
T2I
7
0
Program code can generate interrupts directly. Writing 1 to the correct bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the
interrupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register
is automatically cleared to 0.
Poor coding style that can result in lost interrupt requests:
Good coding style that avoids lost-interrupt requests:
For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail
Trap, and the Watchdog Oscillator Fail Trap, the Interrupt Control registers enable
individual interrupts, set interrupt priorities, and indicate interrupt requests.
The Interrupt Request 0 (IRQ0) register (see
requests for both vectored and polled interrupts. When a request is presented to the
interrupt controller, the corresponding bit in the IRQ0 register becomes 1. If interrupts are
globally enabled (vectored interrupts), the interrupt controller passes an interrupt request
to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can
read the Interrupt Request 0 register to determine if any interrupt requests are pending.
The following coding style used to generate software interrupts by setting bits in the
Interrupt Request registers is not recommended. All incoming interrupts received
between execution of the first LDX command and the final LDX command are lost.
To avoid missing interrupts, use the following coding style to set bits in the Interrupt
Request registers.
R/W
T1I
6
0
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
ORX IRQ0, MASK
R/W
T0I
5
0
P R E L I M I N A R Y
U0RXI
R/W
4
0
FC0H
Table 35
U0TXI
R/W
3
0
on page 75) stores the interrupt
Z8 Encore! XP
R/W
I 2 CI
2
0
Product Specification
SPII
R/W
1
0
®
Interrupt Controller
F1680 Series
ADCI
R/W
0
0
75