Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 239

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
S
Note:
Figure 45. Data Transfer Format—Master Read Transaction with a 7-Bit Address
12. The I
13. The I
14. The software responds by writing the data to be written out to the I
15. The I
16. The I
17. The I
18. If more bytes remain to be sent, return to
19. The software responds by asserting the
20. The I
21. The I
If the slave responds with a Not Acknowledge during the transfer, the I
asserts the
halts. The software terminates the transaction by setting either the
tion) or the
is flushed automatically.
Master Read Transaction with a 7-Bit Address
Figure 45
Follow the steps below for a Master Read operation to a 7-bit addressed slave:
1. The software initializes the
Slave Address
the
ignored.
Register (2nd address byte).
first bit has been sent, the transmit interrupt asserts.
Register.
(or ensuring data bytes, if looping) via the SDA signal.
high period of SCL. The I
If the slave does not acknowledge, see the second paragraph of
transmit interrupt asserts.
SLAVE mode with 7- or 10-bit addressing (the I
mixing of slave address types). The
STOP
2
2
2
2
2
2
2
displays the data transfer format for a Read operation to a 7-bit addressed slave.
C controller loads the I
C controller shifts the second address byte out via the SDA signal. After the
C controller shifts out the remainder of the second byte of the slave address 
C slave sends an Acknowledge by pulling the SDA signal Low during the next
C controller shifts the data out by the SDA signal. After the first bit is sent, the
C controller completes transmission of the data on the SDA signal.
C controller sends a
NCKI
START
and
bit, sets the
NCKI
bit (end this transaction, start a new one). The Transmit Data Register
R = 1
bits. The transaction is complete, and the following steps can be
P R E L I M I N A R Y
ACKV
2
C controller sets the ACK bit in the I
STOP
MODE
A
2
C Shift Register with the contents of the I
bit, clears the
condition to the I
field in the I
MODE
Data
STOP
Step
field selects the address width for 
ACK
bit of the I
2
14.
C Mode Register for MASTER/
2
C bus protocol allows the 
2
bit in the I
C bus.
A
Z8 Encore! XP
2
C Control Register.
Product Specification
2
Data
I2C Master/Slave Controller
C State Register, and
STOP
2
Step
C Status Register. 
2
2
C controller
C Control
®
11.
bit (end transac-
F1680 Series
2
C Data
A
P/S
225