Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 249

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
I
2
C Control Register Definitions
I
2
C Data Register
6. The software responds to the interrupt by reading the I2CISTAT Register clearing the
7. The Master starts the data transfer by asserting SCL Low. After the I
8. After the first bit of the first data byte has been transferred, the I
9. The software responds to the transmit data interrupt by loading the next data byte into
10. The I
11. The bus cycles through
12. The software responds to the
13. When the Master has completed the Acknowledge cycle of the last transfer, it asserts a
14. The Slave I
15. The software responds to the
The I
Shift Register to transmit onto the I
from the Shift Register after it is received from the I
accessible in the Register File address space, but is used only to buffer incoming and
outgoing data.
Writes by the software to the I2CDATA Register are blocked if a slave Write transaction is
underway (the I
SAM
the
data available to transmit, the SCL is released and the master proceeds to shift the first
data byte.
TDRE
the I2CDATA Register.
Acknowledge (or Not Acknowledge, if this byte is the final data byte).
ware has not yet loaded the next data byte when the master brings SCL Low to trans-
fer the most significant data bit, the slave I
register is written.
When a Not Acknowledge is received by the slave, the I
in the I2CISTAT Register, causing the NAK interrupt to be generated.
Register and by asserting the
STOP
the I2CISTAT Register).
clearing the
2
C Data Register listed in
TXI
bit. The software loads the initial data byte into the I2CDATA Register and sets
2
bit which asserts the transmit data interrupt.
or
C Master shifts in the remainder of the data byte. The Master transmits the
bit in the I2CCTL Register.
RESTART
2
2
SPRS
C controller asserts the
C controller is in SLAVE mode, and data is being received).
bit.
condition on the bus.
P R E L I M I N A R Y
Step 7
Table 120
NAK
FLUSH
STOP
to
2
C bus. This register also contains data that is loaded
Step 10
interrupt by clearing the
interrupt by reading the I2CISTAT Register and
STOP/RESTART
bit of the I2CCTL Register.
contains the data that is to be loaded into the
until the final byte is transferred. If the soft-
2
C controller holds SCL Low until the data
2
C bus. The I
Z8 Encore! XP
interrupt (sets the
2
C controller sets the
TXI
Product Specification
I2C Master/Slave Controller
2
C Shift Register is not
bit in the I2CCTL
2
C controller sets the
®
2
C controller has
F1680 Series
SPRS
NCKI
bit in
bit
235