Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 202

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 107. ADC Clock Prescale Register (ADCCP)
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
Bit Position
[0]
DIV2
[1]
DIV4
[2]
DIV8
[3]
DIV16
[7:4]
Caution:
ADC Clock Prescale Register
7
Value (H)
0
1
0
1
0
1
0
1
0h
The ADC Clock Prescale Register
the ADC. When this register is programmed with
ADC Clock. DIV16 has the highest priority, DIV2 has the lowest priority.
The maximum ADC clock at 2.7 V–3.6 V is 5 MHz. The maximum ADC clock at
1.8 V–2.7 V is 2.5 MHz. Set the Prescale Register correctly according to the different
system clocks. See
6
Description
DIV2
Clock is not divided.
System Clock is divided by 2 for ADC Clock.
DIV4
Clock is not divided.
System Clock is divided by 4 for ADC Clock.
DIV8
Clock is not divided.
System Clock is divided by 8 for ADC Clock.
DIV16
Clock is not divided.
System Clock is divided by 16 for ADC Clock.
Reserved—Must be 0.
Reserved
0
Table 196
5
P R E L I M I N A R Y
on page 349 for details.
(Table
4
F76H
R/W
107) is used to provide a divided system clock to
DIV16
3
0
0h
, the System Clock is used for the
Z8 Encore! XP
DIV8
2
0
Product Specification
Analog-to-Digital Converter
DIV4
1
0
®
F1680 Series
DIV2

0
0

188