Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 222

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Caution:
10 = Transmit Only Mode
11 = Transmit/Receive Mode
BRGCTL—Baud Rate Generator Control
The function of this bit depends upon ESPIEN1,0. When ESPIEN1,0 = 00, this bit allows
enabling the BRG to provide periodic interrupts.
If the ESPI is disabled
0 = The Baud Rate Generator timer function is disabled. 
1 = The Baud Rate Generator timer function and timeout interrupt is enabled. 
If the ESPI is enabled
0 = Reading the Baud Rate High and Low registers returns the BRG Reload value.
1 = Reading the Baud Rate High and Low registers returns the BRG Counter value.
PHASE—Phase Select
Sets the phase relationship of the data to the clock. For more information on 
operation of the PHASE bit, see
CLKPOL—Clock Polarity
0 = SCK idles Low (0).
1 = SCK idles High (1).
WOR—Wire-OR (Open-Drain) Mode Enabled
0 = ESPI signal pins not configured for open-drain.
1 = All four ESPI signal pins (SCK, SS, MISO, and MOSI) configured for 
MMEN—ESPI Master Mode Enable
This bit controls the data I/O pin selection and SCK direction
0 = Data out on MISO, data in on MOSI (used in SPI SLAVE mode), SCK is an input.
1 = Data out on MOSI, data in on MISO (used in SPI MASTER mode), SCK is an output.
If reading the counter one byte at a time while the BRG is counting keep in
mind that the values will not be in sync. It is recommended to read the
counter using word (2 byte) reads.
If MMEN = 1, the BRG is enabled to generate SCK. If MMEN = 0 the BRG is
enabled to provide a Slave SCK timeout. See the Slave Abort error description.
open-drain function. This setting is typically used for multi-Master and/or 
Multi-Slave configurations.
Reading the Baud Rate High and Low registers returns the BRG Reload value.
Reading the Baud Rate High and Low registers returns the BRG Counter value.
If MMEN = 1, the BRG is enabled to generate SCK. If MMEN = 0, the BRG is 
disabled.
Use this setting if the software application is both sending and receiving information.
Use this setting in MASTER or SLAVE mode when the software application is 
sending data but not receiving. RDRNE will not assert.
Both TDRE and RDRNE will be active.
P R E L I M I N A R Y
ESPI Clock Phase and Polarity Control
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Product Specification
on page 195.
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F1680 Series
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208