Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 215

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Figure 40. ESPI Configured as an SPI Master in a Single Master, Multiple Slave System
Figure 39. ESPI Configured as an SPI Master in a Single Master, Single Slave System
To Slave #2’s SS Pin
To Slave #1’s SS Pin
To Slave’s SS Pin
Multi-Master SPI Operation
In a Multi-Master SPI system, all SCK pins are tied together, all MOSI pins are tied
together, and all MISO pins are tied together. All SPI pins must be configured in 
open-drain mode to prevent bus contention. At any time, only one SPI device is
configured as the Master and all other devices on the bus are configured as slaves. The
Master asserts the SS pin on the selected slave. Then, the active Master drives the clock
and transmits data on the SCK and MOSI pins to the SCK and MOSI pins on the Slave
(including those Slaves which are not enabled). The enabled slave drives data out its
MISO pin to the MISO Master pin.
From Slave
From Slaves
To Slave
To Slave
To Slaves
To Slaves
MISO
MOSI
SCK
SS
P R E L I M I N A R Y
MISO
MOSI
SCK
GPIO
GPIO
Bit 0
Bit 0
8-bit Shift Register
8-bit Shift Register
ESPI Master
ESPI Master
Bit 7
Baud Rate
Generator
Bit 7
Baud Rate
Generator
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Product Specification
®
F1680 Series
201