Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 257

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 128. I2CSTATE_L
Table 129. I
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
State
I2CSTATE_H
0000–0100
0110–0111
0101
1000–1111
I
Reserved
2
2
C Mode Register
C Mode Register (I2C Mode = F56H)
R
7
0
Substate
I2CSTATE_L
0000
0000
0000
0001
0111
0110
0101
0100
0011
0010
0001
0000
1000
The I
ing mode, slave address and diagnostic modes.
MODE—Selects the I
00 = MASTER/SLAVE capable (supports multi-master arbitration) with 7-bit 
2
C Mode Register (see
6
MODE[1:0]
Substate Name
—
—
Master Start
Master Restart
Send/Receive bit 7
Send/Receive bit 6
Send/Receive bit 5
Send/Receive bit 4
Send/Receive bit 3
Send/Receive bit 2
Send/Receive bit 1
Send/Receive bit 0
Send/Receive
Acknowledge
R/W
0
2
5
C controller operational mode
P R E L I M I N A R Y
Table
R/W
IRM
129) provides control over master versus slave operat-
4
0
F56H
There are no substates for these
There are no substates for these 
Sending/Receiving most significant bit
State Description
I2CSTATE_H values.
I2CSTATE_H values.
Initiating a new transaction
Master is ending one transaction and starting a
new one without letting the bus go idle.
Sending/Receiving least significant bit
Sending/Receiving Acknowledge
GCE
R/W
3
0
Z8 Encore! XP
2
SLA[9:8]
R/W
Product Specification
I2C Master/Slave Controller
0
1
®
F1680 Series
DIAG
R/W
0
0
243