Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 250

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 120. I
BITS
FIELD
RESET
R/W
ADDR
Table 121. I2C Interrupt Status Register (I2CISTAT = F51H)
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
Bit Position
[7:0] DATA
I
2
2
C Interrupt Status Register
Data 7
C Data Register (I2CDATA = F50H)
TDRE
R/W
R
7
0
7
1
The Read-only I
current I
interrupt occurs, one or more of the
is set. The
associated with the
TDRE—Transmit Data Register Empty
When the I
When set, this bit causes the I
controller is shifting in data during the reception of a byte or when shifting an address and
the RD bit is set. This bit clears by writing to the I2CDATA Register.
RDRF—Receive Data Register Full
This bit is set = 1 when the I
byte of data. When asserted, this bit causes the I
bit clears by reading the I2CDATA Register.
SAM—Slave Address Match
This bit is set = 1 if the I
received that matches the unique slave address or General Call Address (if enabled by the
GCE
Value
I
2
C Data Byte
bit in the I
2
Data 6
RDRF
C interrupt and provides status of the I
R/W
GCA
2
R
6
0
6
0
C controller is enabled, this bit is 1 when the I
Description
2
and
C Mode Register). In 10-bit addressing mode, this bit is not set until a
2
C Interrupt Status Register (see
SAM
RD
Data 5
SAM
R/W
R
bits do not generate an interrupt but rather provide status 
5
0
5
0
bit interrupt.
2
C controller is enabled in SLAVE mode and an address is
P R E L I M I N A R Y
2
C controller is enabled and the I
2
C controller to generate an interrupt, except when the I
Data 4
GCA
R/W
R
4
0
4
0
TDRE
F50H
F51H
,
RDRF
Data 3
R/W
RD
R
2
3
0
3
0
2
,
C controller to generate an interrupt. This
C controller
Table
SAM
,
ARBLST
121) indicates the cause of any
Z8 Encore! XP
ARBLST
Data 2
R/W
2
C Data Register is empty.
R
2
0
2
0
.
2
When an 
C controller has received a
,
Product Specification
SPRS
I2C Master/Slave Controller
Data 1
SPRS
R/W
or
R
1
0
1
0
®
NCKI
F1680 Series
bits 
Data 0
NCKI
R/W
R
0
0
0
0
2
C
236