Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 216

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
From Master
From Master
From Master
When the ESPI is configured as a Master in a Multi-Master SPI system, the SS pin must
be configured as an input. The SS input signal on a device configured as a Master should
remain High. If the SS signal on the active Master goes Low (indicating another 
Master is accessing this device as a Slave), a Collision error flag is set in the ESPI Status
register. The Slave select outputs on a Master in a Multi-Master system must come from
GPIO pins.
SPI Slave Operation
The ESPI block is configured for SLAVE mode operation by setting the MMEN bit = 0 
in the ESPICTL register, and setting the SSIO bit = 0 in the ESPIMODE register. 
The SSMD field of the ESPI Mode register is set to 00 for SPI protocol mode. The
PHASE, CLKPOL, and WOR bits in the ESPICTL register and the NUMBITS 
field in the ESPIMODE register must be set to be consistent with the other 
SPI devices. Typically for an SPI Slave, SSPO = 0.
If the Slave has data to send to the Master, the data must be written to the Data 
register before the transaction starts (first edge of SCK when SS is asserted). 
If the Data register is not written prior to the Slave transaction, the MISO pin 
outputs all 1’s.
Due to the delay resulting from synchronization of the SS and SCK input signals to 
the internal system clock, the maximum SCK baud rate that can be supported in SLAVE
mode is the system clock frequency divided by 4. This rate is controlled by the 
SPI Master.
To Master
Figure 41
Figure 41. ESPI Configured as an SPI Slave
SS
MISO
MOSI
SCK
displays the ESPI configuration in SPI SLAVE mode.
P R E L I M I N A R Y
Bit 7
8-bit Shift Register
SPI Slave
Bit 0
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Product Specification
®
F1680 Series
202