Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 184

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
LIN Control Register
When
operation. A more detailed discussion of each bit follows the table.
Table 92. LIN Control Register (U0CTL1 = F43H with MSEL = 010b)
BITS
FIELD
RESET
CPU ACCESS
ADDR
Note: R/W = Read/Write
Bit Position
7
LMST
6
LSLV
5
ABEN
4
ABIEN
[3:2]
LinState[1:0]
MSEL
=
010b
LMST
Value
LIN MASTER Mode
0
1
LIN SLAVE Mode
0
1
Autobaud Enable
0
1
Autobaud Interrupt Enable
0
1
LIN State Machine
00
01
10
11
R/W
, the LIN Control Register provides control for the LIN mode of 
7
0
LSLV
P R E L I M I N A R Y
R/W
6
0
Description
LIN MASTER mode not selected.
LIN MASTER mode selected (if MPEN, PEN, LSLV = 0).
LIN SLAVE mode not selected.
LIN SLAVE mode selected (if MPEN, PEN, LMST = 0).
Autobaud not enabled.
Autobaud enabled, if in LIN SLAVE mode.
Interrupt following autobaud does not occur.
Interrupt following autobaud enabled, if in LIN SLAVE
mode. When the autobaud character is received, a receive
interrupt is generated and the ATB bit is set in the Status0
Register.
Sleep state (either LMST or LSLV can be set).
Wait for Break state (only valid for LSLV = 1).
Autobaud state (only valid for LSLV = 1).
Active state (either LMST or LSLV can be set).
ABEN
R/W
5
0
ABIEN
R/W
F43H, F4BH
4
0
R/W
Z8 Encore! XP
LinState[1:0]
3
0
Product Specification
R/W
2
0
®
TxBreakLength
R/W
F1680 Series
1
0
LIN-UART
R/W
0
0
170