Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 297

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
Table 160. Read Status Byte
BITS
FIELD
DEFAULT
VALUE
Note:
Byte Read
To read a byte from the NVDS array, user code must first push the address onto the stack.
User code issues a
the return from the sub-routine, the read byte resides in working register R0, and the read
status byte resides in working register R1. The bit fields of this status byte are defined in
Table
The read routine uses 16 bytes of stack space in addition to the 1 byte of address pushed by
you. Sufficient memory must be available for this stack usage. Because of the Flash mem-
ory architecture, NVDS reads exhibit a non-uniform execution time. A read operation
takes between 71 s and 258 s (assuming a 20 MHz system clock). Slower system clock
speeds result in proportionally higher execution times.
NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return
0xff. Illegal read operations have a 6 s execution time. The status byte returned by the
NVDS read routine is zero for successful read. If the status byte is non-zero, there is 
a corrupted value in the NVDS array at the location being read. In this case, the value
returned in R0 is the byte most recently written to the array that does not have an error.
When the NVDS array size is 256 bytes, there is no address exceeding the size, the
bit is of no use.
7
0
Reserved—Must be 0.
DE—Data Error
When reading a NVDS address, if an error is found in the latest data corresponding to
this NVDS address, this bit is set to 1. NVDS source code steps forward until finding
a valid data at this address.
FE—Flash Error
If Flash error is detected, this bit is set to 1.
IGADDR—Illegal address
When NVDS byte reads from invalid addresses (those exceeding the NVDS array
size) occur, this bit is set to 1.
160. Also, the user code should pop the address byte off the stack.
Reserved
6
0
CALL
instruction to the address of the byte-read routine
5
0
P R E L I M I N A R Y
DE
4
0
Reserved
3
0
Z8 Encore! XP
FE
2
0
Product Specification
Non-Volatile Data Storage
IGADDR Reserved
0
1
®
F1680 Series
(0x4000
IGADDR
0
0
). At
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