Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 213

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

®
Z8 Encore! XP
F1680 Series
Product Specification
199
Synchronous Frame Sync Pulse Mode
This mode is selected by setting the SSMD field of the Mode Register to 10. This mode is
typically used for continuous transfer of fixed length frames where the frames are
delineated by a pulse of duration one SCK period. The SSV bit in the ESPI Transmit Data
Command register does not control the SS pin directly in this mode. SSV must be set
before or in sync with the first transmit data byte being written. The SS signal will assert 1
SCK cycle before the first data bit and will stop after 1 SCK period. SCK is active from
the initial assertion of SS until the transaction end due to lack of transmit data.
The transaction is terminated by the Master when it no longer has data to send. If 
TDRE=1 at the end of a character, the SS output will remain detached and SCK stops after
the last bit is transferred. The TUND bit (transmit underrun) will assert in this case. Once
the transaction has completed, hardware will clear the SSV bit.
Figure 37
displays a frame
with synchronous frame sync pulse mode.
SCK (SSMD = 10,
PHASE = 0,
CLKPOL = 0,
SSPO = 1)
Bit7
Bit6
Bit1
Bit0
Bit7
Bit 6
MOSI, MISO
SS
SSV
Figure 37. Synchronous Frame Sync Pulse mode (SSMD = 10)
Synchronous Framing with SS Mode
This mode is selected by setting the SSMD field of the Mode Register to 11.
Figure 38
on
page 200 displays synchronous message framing mode with SS alternating between
consecutive frames. A frame consists of a fixed number of data bytes as defined by
2
software. An example of this mode is the Inter-IC Sound (I
S) protocol which is used to
transfer left/right channel audio data. The SSV indicates whether the corresponding bytes
are left or right channel data. The SSV value must be updated when servicing the 
TDRE interrupt/request for the first byte in a left or write channel frame. This can be
PS025011-1010
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface