Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 144

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 73. Multi-Channel Timer Control 0 Register (MCTCTL0)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Multi-Channel Timer Control 0, Control 1 Registers
7
TCTST
R/W1C
0
The Multi-Channel Timer Control registers (MCTCTL0, MCTCTL1) control 
Multi-Channel Timer operation. Writes to the PRES field of MCTCTL1 register are
buffered when TEN = 1, and will not take effect until the next end of cycle count occurs.
TCTST—Timer Count Status
This bit indicates if a timer count cycle is complete and is cleared by writing 1 to the bit
and is cleared when TEN = 0.
0 = Timer count cycle is not complete.
1 = Timer count cycle is complete.
CHST—Channel Status
This bit indicates if a channel Capture/Compare event occurred. This bit is the logical OR
of the CHyEF bits in the MCTCHS1 register. This bit is cleared when TEN=0.
0 = No channel capture/compare event has occurred.
1 = A channel capture/compare event has occurred. One or more of the CHDEF, 
TCIEN—Timer Count Interrupt Enable
This bit enables generation of timer count interrupt. A timer count interrupt is generated
whenever the timer completes a count cycle: counting up to Reload Register value or
counting down to zero depending on whether the TIMER mode is Count Modulo or 
Count up/down. 
0 = Timer Count Interrupt is disabled.
1 = Timer Count Interrupt is enabled.
TCLKS—Timer Clock Source 
000 = System Clock (Prescaling enabled)
001 = Reserved
010 = System Clock gated by active High Timer Input signal (Prescaling enabled).
011 = System Clock gated by active Low Timer Input signal (Prescaling enabled).
100 = Timer I/O pin input rising edge (Prescaler disabled).
101 = Timer I/O pin input falling edge (Prescaler disabled).
110 = Reserved.
111 = Reserved.
CHCEF, CHBEF, and CHAEF bits in the MCTCHS1 register are set.
6
CHST
00H in Sub-Address Register, accessible through SubRegister 0
R
0
5
TCIEN
R/W
0
P R E L I M I N A R Y
4
Reserved Reserved
R
0
3
R
0
2
Z8 Encore! XP
R/W
0
Product Specification
1
TCLKS
R/W
0
Multi-Channel Timer
®
F1680 Series
0
R/W
0
130