Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 142

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 69. MCT Reload High Byte Register (MCTRH)
Table 70. MCT Reload Low Byte Register (MCTRL)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
MCT Reload High and Low Byte Registers
R/W
R/W
7
1
7
1
When MCT is enabled, a read from MCTH causes the value in MCTL to be stored in a
temporary holding register. A read from MCTL returns this temporary register when MCT
is enabled. When MCT is disabled, reads from MCTL read the register directory. 
The MCT High and Low byte registers are not reset when TEN = 0.
MCTH and MCTL—MCT High and Low Bytes
These 2 bytes, {MCTH[7:0], MCTL[7:0]}, contain the current 16-bit MCT count value.
The MCT Reload High and Low Byte (MCTRH and MCTRL) registers (see
Table
writes to this address update the register on the next clock cycle. When TEN = 1 writes to
this register are buffered and transferred into the register when the counter reaches the end
of the count cycle.
Up Down Mode Period
Modulo Mode Period
70) store a 16-bit reload value, {MCTRH[7:0], MCTRL[7:0]}. When TEN = 0,

R/W
R/W
6
1
6
1
R/W
R/W
5
1
5
1
=
P R E L I M I N A R Y
=
Prescaler
--------------------------------------------------------------------------------------- -
2 Prescaler Reload Value
---------------------------------------------------------------------------------- -

R/W
R/W
4
1
4
1
MCTRH
MCTRL

FA2H
FA3H

f
f
MCTclk
Reload Value
MCTclk

R/W
R/W
3
1
3
1
Z8 Encore! XP
+
1
R/W
R/W

2
1
2
1
Product Specification
R/W
R/W
Multi-Channel Timer
1
1
1
1
®
F1680 Series
Table 69
R/W
R/W
0
1
0
1
and
128