Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 94

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
IRQ2 Enable High and Low Bit Registers
PA7VENL
R/W
7
0
PA7VENH—Port A Bit[7] or LVD Interrupt Request Enable High Bit.
PA6C0ENH—Port A Bit[6] or Comparator 0 Interrupt Request Enable High Bit.
PA5C1ENH—Port A Bit[5] or Comparator 1 Interrupt Request Enable High Bit.
PADxENH—Port A or Port D Bit[x] (x=1, 2, 3, 4) Interrupt Request Enable High Bit.
PA0ENH—Port A Bit[0] Interrupt Request Enable High Bit. 
See Interrupt Port Select register for selection of either Port A or Port D as 
the interrupt source.
PA7VENL—Port A Bit[7] or LVD Interrupt Request Enable Low Bit.
PA6C0ENL—Port A Bit[6] or Comparator 0 Interrupt Request Enable Low Bit.
PA5C1ENL—Port A Bit[5] or Comparator 1 Interrupt Request Enable Low Bit.
PADxENL—Port A or Port D Bit[x] (x=1, 2, 3, 4) Interrupt Request Enable Low Bit.
PA0ENL—Port A Bit[0] Interrupt Request Enable Low Bit.
Table 44
registers (see
interrupts in the Interrupt Request 2 register. Priority is generated by setting bits in each
register.
Table 44. IRQ2 Enable and Priority Encoding
Note: x indicates the register bits from 0–7.
IRQ2ENH[x] IRQ2ENL[x] Priority
PA6C0ENL
describes the priority control for IRQ2. The IRQ2 enable High and Low Bit
R/W
0
0
1
1
6
0
Table 45
PA5C1ENL PAD4ENL PAD3ENL PAD2ENL PAD1ENL PA0ENL
and
R/W
5
0
Table 46
0
1
0
1
P R E L I M I N A R Y
Disabled
Level 1
Level 2
Level 3
on page 81) form a priority encoded enabling for
R/W
4
0
FC5H
R/W
3
0
Description
Disabled
Low
Nominal
High
Z8 Encore! XP
R/W
2
0
Product Specification
R/W
®
1
0
Interrupt Controller
F1680 Series
R/W
0
0
80