Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 314

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 164. OCD Control Register (OCDCTL)
.
BITS
FIELD
RESET
R/W
PS025011-1010
DBGMODE
R/W
7
0
A “reset and stop” function can be achieved by writing
go” function is achieved by writing
a “run” function is implemented by writing
DBGMODE—DEBUG Mode
Setting this bit to 1 causes the device to enter DEBUG mode. When in DEBUG mode, 
the eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to
resume execution. This bit is automatically set when a BRK instruction is decoded and
Breakpoints are enabled.
0 = The device is running (operating in NORMAL mode).
1 = The device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of
are disabled and the
instruction is decoded, the OCD takes action depending upon the BRKLOOP bit. 
0 = BRK instruction is disabled. 
1 = BRK instruction is enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
a Debug Acknowledge character (
automatically clears itself when an acknowledge character is sent.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
BRKLOOP—Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded and
breakpoints are enabled (BRKEN is 1). If this bit is 0, the DBGMODE bit is automatically
set to 1 and the OCD enters DEBUG mode. If BRKLOOP is set to 1, the eZ8 CPU loops
on the BRK instruction. 
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
BRKPC—Break when PC == OCDCNTR
If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR register, DBGMODE is auto-
matically set to 1. If this bit is set, the OCDCNTR register does not count when the CPU is
running.
BRKEN
R/W
6
0
DBGACK BRKLOOP
BRK
R/W
5
0
instruction behaves like a NOP. If this bit is set to 1 and a
P R E L I M I N A R Y
BRK
R/W
FFH
4
0
41H
instruction (opcode
) to the host when a Breakpoint occurs. This bit
to this register. If the device is in DEBUG mode,
40H
BRKPC
R/W
3
0
to this register.
81H
BRKZRO
Z8 Encore! XP
00H
R/W
2
0
to this register. A “reset and
). By default, Breakpoints
Product Specification
Reserved
R/W
1
0
®
On-Chip Debugger
F1680 Series
RST
R/W
BRK
0
0
300