Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 372

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
(Output)
(Output)
TXD
(Input)
Table 207. UART Timing with CTS
Parameter
UART
T
T
T
CTS
1
2
3
DE
UART Timing
Figure 78
CTS is used for flow control. The CTS to DE assertion delay (T1) assumes that the trans-
mit data register has been loaded with data prior to CTS assertion.
Figure 79
case where CTS is not used for flow control. DE asserts after the transmit data register has
been written. DE remains asserted for multiple characters as long as the transmit data 
register is written with the next character before the current character has completed.
bit 7
Abbreviation
CTS Fall to DE output delay
DE assertion to TXD falling edge (start bit) delay ± 5
End of Stop Bit(s) to DE deassertion delay
parity
and
and
Table 207
Table 208
stop
Figure 78. UART Timing With CTS
end of
stop bit(s)
T 3
provide timing information for UART pins for the case where
on page 359 provide timing information for UART pins for the
P R E L I M I N A R Y
T 1
2 * XIN period 2 * XIN period
± 5
Z8 Encore! XP
Min
T 2
Delay (ns)
Product Specification
start
Electrical Characteristics
+ 1 bit time
®
Max
F1680 Series
bit 0
bit 1
358