Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 56

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 11. Reset Status Register (RSTSTAT)
Reset Register Definitions
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
Reset or Stop Mode Recovery Event
Power-On Reset or VBO Reset
Reset using RESET pin assertion
Reset using Watchdog Timer timeout
Reset using the On-Chip Debugger (OCTCTL[1] set to 1)
Reset from STOP mode using DBG Pin driven Low
Stop Mode Recovery using GPIO pin transition
Stop Mode Recovery using Watchdog Timer timeout
Reset Status Register
POR/VBO
R
7
The Reset Status (RSTSTAT) register is a read-only register which indicates the source of
the most recent Reset event, a Stop Mode Recovery event, and a WDT timeout. Reading
this register resets the upper 4 bits to 0.
This register shares its address with the Reset Status register, which is write-only 
(see
POR/VBO—Power-On initiated VBO Reset or general VBO Reset Indicator
If this bit is set to 1, a POR or VBO Reset event occurs. This bit is reset to 0, if a WDT
timeout or Stop Mode Recovery occurs. This bit is also reset to 0 when the register is read.
STOP—Stop Mode Recovery Indicator
If this bit is set to 1, a Stop Mode Recovery occurs. If the STOP and WDT bits are both set
to 1, the Stop Mode Recovery occurs because of a WDT timeout. If the STOP bit is 1 and
the
reset by Power-On Reset or WDT timeout that occurred while not in STOP mode. Reading
this register also resets this bit.
See descriptions below
WDT
Table
STOP
bit is 0, the Stop Mode Recovery is not caused by a WDT timeout. This bit is
11).
R
6
WDT
R
5
P R E L I M I N A R Y
EXT
R
4
0
FF0H
R
3
0
Reset, Stop Mode Recovery, and Low-Voltage
POR
Reserved
Z8 Encore! XP
1
0
0
1
1
0
0
R
2
0
STOP
Product Specification
0
0
0
0
0
1
1
R
1
0
®
WDT
F1680 Series
0
0
1
0
0
0
1
LVD
EXT
R
0
0
0
1
0
0
0
0
0
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