Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 224

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

Table 114. ESPI Status Register (ESPISTAT)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Note: R/W* = Read access. Write a 1 to clear the bit to 0.
ESPI Status Register
TDRE
R
7
1
NUMBITS[2:0]—Number of Data Bits Per Character to Transfer
This field contains the number of bits to shift for each character transfer. For information
on valid bit positions when the character length is less than 8 bits, see description of
Data Register
000 = 8 bits
001 = 1 bit
010 = 2 bits
011 = 3 bits
100 = 4 bits
101 = 5 bits
110 = 6 bits
111 = 7 bits
SSIO—Slave Select I/O
This bit controls the direction of the SS pin. In single MASTER mode, SSIO is set to 1
unless a separate GPIO pin is being used to provide the SS output function. In the SPI
Slave or multi-Master configuration, SSIO is set to 0.
0 = SS pin configured as an input (SPI Slave and multi-Master modes).
1 = SS pin configured as an output (SPI single Master mode).
SSPO—Slave Select Polarity
This bit controls the polarity of the SS pin.
0 = SS is active Low. (SSV = 1 corresponds to SS = 0).
1 = SS is active High. (SSV = 1 corresponds to SS = 1).
The ESPI Status register
to their Reset state if the ESPI is disabled.
TDRE—Transmit Data Register Empty
0 = Transmit data register is full or ESPI is disabled.
1 = Transmit data register is empty. A write to the ESPI (Transmit) Data register
clears this bit.
TUND
R/W*
6
0
on page 205.
R/W*
COL
5
0
(Table
P R E L I M I N A R Y
114) indicates the current state of the ESPI. All bits revert
R/W*
ABT
4
0
F64H
ROVR
R/W*
3
0
RDRNE
Z8 Encore! XP
Enhanced Serial Peripheral Interface
R
2
0
Product Specification
TFST
R
1
0
®
F1680 Series
SLAS
R
0
1
ESPI
210