Z8F2480AN020SG Zilog, Z8F2480AN020SG Datasheet - Page 246

• Manufacturer Part Number: Z8F2480AN020SG
• Description: MCU 8BIT 24KB FLASH 44LQFP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2480AN020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 37
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LQFP
• Processor Series: Z8F248x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4676

PS025011-1010
S
Slave Address
2. The Master initiates a transfer, sending the first address byte. The I
3. The Master sends the second address byte. The SLAVE mode I
4. The software responds to the interrupt by reading the I2CISTAT Register, which 
5. The Master detects the Acknowledge and sends the first byte of data.
6. The I
7. The software responds by reading the I2CISTAT Register, finding the
8. The Master and Slave loops through
9. The Master sends the
Slave Transmit Transaction With 7-bit Address
The data transfer format for a master reading data from a slave in 7-bit address mode 
is displayed in
Controller operating as a slave in 7-bit addressing mode and transmitting data to the bus
master.
Figure 49. Data Transfer Format—Slave Transmit Transaction with 7-bit Address
recognizes the start of a 10-bit address with a match to
R/W bit = 0 (a Write from the master to the slave). The I
indicating it is available to accept the transaction.
address match between the second address byte and
I2CISTAT Register is set to 1, thereby causing an interrupt. The
indicating a Write to the slave. The I
available to accept the data.
clears the
until the first byte of data is received. If the software is only able to accept a single
byte, it sets the
Acknowledge, depending on the state of the
controller generates the receive data interrupt by setting the
Register.
and then reading the I2CDATA Register, which clears the
accept only one more data byte, it sets the
Not Acknowledge instruction or runs out of data to send.
cause the I
I2CISTAT Register). Because the slave received data from the master, the software
takes no action in response to the STOP interrupt other than reading the I2CISTAT
Register to clear the
2
C controller receives the first byte and responds with Acknowledge or Not
SAM
2
Figure
C controller to assert the STOP interrupt (the
bit. Because
NAK
49. The procedure that follows describes the I
R = 1
bit in the I2CCTL Register.
STOP
STOP
P R E L I M I N A R Y
bit.
RD
or
A
RESTART
= 0, no immediate action is taken by the software 
2
Step 5
C controller acknowledges, indicating it is
Data
signal on the bus. Either of these signals can
NAK
to
NAK
Step 7
bit in the I2CCTL Register.
bit in the I2CCTL Register. The I
A
Z8 Encore! XP
SLA[7:0]
until the Master detects a 
SLA[9:8]
2
RDRF
STOP
C controller acknowledges,
Data
RDRF
Product Specification
I2C Master/Slave Controller
2
C controller detects an
. The
bit. If the software can
bit = 1 in the
2
RD
C Master/Slave 
bit in the I2CISTAT
and detects 
2
bit is cleared to 0,
C controller 
®
A
SAM
RDRF
F1680 Series
bit in the
bit = 1,
P/S
2
C
232